Multichannel memory to augment local memory

Abstract

A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.

What is claimed is: 
     
       1. A memory system configured to augment a capacity of a plurality of main scratchpads for a plurality of respective processing cores, the memory system comprising:
 a global memory device coupled to a plurality of processing elements, wherein the global memory device is positioned external to a chip on which the plurality of processing elements reside; 
 at least one main scratchpad coupled to at least one processing element of the plurality of processing elements and the global memory device; and 
 a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device, wherein at least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device. 
 
     
     
       2. The memory system of  claim 1 , wherein:
 the plurality of auxiliary scratchpads are configured as dynamic random access memory (DRAM). 
 
     
     
       3. The memory system of  claim 2 , wherein:
 the plurality of auxiliary scratchpads define a multichannel auxiliary DRAM array. 
 
     
     
       4. The memory system of  claim 3 , wherein:
 the plurality of processing elements comprises a plurality of processing cores; 
 each auxiliary scratchpad of the plurality of auxiliary scratchpads is coupled to a respective processing core of the plurality of processing cores, thereby defining a plurality of auxiliary scratchpad channels. 
 
     
     
       5. The memory system of  claim 4  further comprising:
 a channel controller coupled to one or more auxiliary scratchpads of the plurality of auxiliary scratchpads, thereby further defining an auxiliary scratchpad channel of the plurality of auxiliary scratchpad channels. 
 
     
     
       6. The memory system of  claim 1  further comprising:
 a plurality of chiplets, wherein each chiplet of the plurality of chiplets comprises:
 the at least one main scratchpad; 
 the at least one processing element; and 
 one or more auxiliary scratchpads of the plurality of auxiliary scratchpads. 
 
 
     
     
       7. The memory system of  claim 1  further comprising:
 an on-chip interconnect coupled to each of the global memory device, at least one processing element of the plurality of processing elements, the at least one main scratchpad, and the plurality of auxiliary scratchpads. 
 
     
     
       8. A method of assembling a memory system configured to augment a capacity of a plurality of main scratchpad for a plurality of respective processing cores, the method comprising:
 positioning a plurality of processing elements on a chip; 
 coupling a global memory device to the plurality of processing elements, wherein the global memory device is positioned external to the chip; 
 coupling at least one main scratchpad to at least one processing element of the plurality of processing elements and the global memory device; and 
 coupling a plurality of auxiliary scratchpads to the plurality of processing elements and the global memory device, wherein at least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device. 
 
     
     
       9. The method of  claim 8  further comprising:
 configuring the plurality of auxiliary scratchpads as dynamic random access memory (DRAM). 
 
     
     
       10. The method of  claim 9  further comprising:
 assembling the plurality of auxiliary scratchpads to define a multichannel auxiliary DRAM array. 
 
     
     
       11. The method of  claim 10  further comprising:
 coupling each auxiliary scratchpad of the plurality of auxiliary scratchpads to a respective processing core of the plurality of processing cores, thereby defining a plurality of auxiliary scratchpad channels. 
 
     
     
       12. The method of  claim 11  further comprising:
 coupling a channel controller to one or more auxiliary scratchpads of the plurality of auxiliary scratchpads, thereby further defining an auxiliary scratchpad channel of the plurality of auxiliary scratchpad channels. 
 
     
     
       13. The method of  claim 8  further comprising:
 assembling a plurality of chiplets, wherein each chiplet of the plurality of chiplets includes:
 the at least one main scratchpad; 
 the at least one processing element; and 
 one or more auxiliary scratchpads of the plurality of auxiliary scratchpads. 
 
 
     
     
       14. A computer system configured to augment a capacity of a plurality of main scratchpads for a plurality of respective processing core, the computer system comprising:
 a plurality of processing devices positioned on a chip, each processing device of the plurality of processing devices comprises:
 one or more processing elements; and 
 at least one main scratchpad coupled to the one or more processing elements; 
 
 a global memory device coupled to the plurality of processing devices, wherein the global memory device is positioned external to the chip, the global memory device coupled to the at least one main scratchpad; and 
 a plurality of auxiliary scratchpads coupled to the plurality of processing devices and the global memory device, wherein at least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device. 
 
     
     
       15. The computer system of  claim 14 , wherein:
 the plurality of auxiliary scratchpads are configured as dynamic random access memory (DRAM). 
 
     
     
       16. The computer system of  claim 15 , wherein:
 the plurality of auxiliary scratchpads define a multichannel auxiliary DRAM array. 
 
     
     
       17. The computer system of  claim 16 , wherein:
 the plurality of processing devices comprise a plurality of processing cores; 
 each auxiliary scratchpad of the plurality of auxiliary scratchpads is coupled to a respective processing core of the plurality of processing cores, thereby defining a plurality of auxiliary scratchpad channels. 
 
     
     
       18. The computer system of  claim 17  further comprising:
 a channel controller coupled to one or more auxiliary scratchpads of the plurality of auxiliary scratchpads, thereby further defining an auxiliary scratchpad channel of the plurality of auxiliary scratchpad channels. 
 
     
     
       19. The computer system of  claim 14  further comprising:
 a plurality of chiplets, wherein each chiplet of the plurality of chiplets comprises:
 the at least one main scratchpad; 
 the at least one processing device; and 
 one or more auxiliary scratchpads of the plurality of auxiliary scratchpads. 
 
 
     
     
       20. The computer system of  claim 14  further comprising:
 an on-chip interconnect coupled to each of the global memory device, at least one processing element of the plurality of processing elements, the at least one main scratchpad, and the plurality of auxiliary scratchpads.