Inventor

SRINIVASAN VIJAYALAKSHMI

US85 patents

⚠️ This page may combine multiple inventors who share the name “SRINIVASAN VIJAYALAKSHMI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SRINIVASAN VIJAYALAKSHMI

IBM

Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Iterative write pausing techniques to improve read latency of memory systems

Branch history guided instruction/data prefetching

Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Method and apparatus for prefetching branch history information

Cost-conscious pre-emptive cache line displacement and relocation mechanisms

Processor with low overhead predictive supply voltage gating for leakage power reduction

Method and apparatus for an efficient multi-path trace cache design

Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits

Private memory table for reduced memory coherence traffic

Private memory table for reduced memory coherence traffic

Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM)

Multi-threaded processor instruction balancing through instruction uncertainty

Sectored cache memory

Methods involving memory caches

Systems and methods for mutually exclusive activation of microprocessor resources to control maximum power

Loop management in multi-processor dataflow architecture

Method and system for integrating SRAM and DRAM architecture in set associative cache

Method and system of peak power enforcement via autonomous token-based control and management

Context look ahead storage structures

Context look ahead storage structures

Pre-computation slice merging for prefetching in a computer processor

System-aware selective quantization for performance optimized distributed deep learning

Predicting cache misses using data access behavior and instruction address

Processor with memory-embedded pipeline for table-driven computation

Single thread cache miss rate estimation

Matrix multiplication on a systolic array

Matrix multiplication on a systolic array

Sparse systolic array design

Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction

Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits

Thread-based cache content saving for task switching

Thread-based cache content saving for task switching

Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers

Method and system for providing an improved store-in cache

Method to reduce the number of times in-flight loads are searched by store instructions in a multi-threaded processor

Limiting entries searched in load reorder queue to between two pointers for match with executing load instruction

Multichannel memory to augment local memory

Hybrid data-model parallelism for efficient deep learning

Dynamically resizing minibatch in neural network execution

Bi-scaled deep neural networks

Methods of cache preloading on a partition or a context switch

Methods of cache preloading on a partition or a context switch

Non-data inclusive coherent (NIC) directory for cache

Non-data inclusive coherent (NIC) directory for cache

EMMA PHILIP G

Processor core stacking for efficient collaboration

KHUBAIB KHUBAIB

Reducing broadcasts in multiprocessors

SRINIVASAN VIJAYALAKSHMI

Predicting cache misses using data access behavior and instruction address

BURCEA IOANA MONICA

Predicting out-of-order instruction level parallelism of threads in a multi-threaded processor