Inventor

COLOMBEAU BENJAMIN

US52 patents

⚠️ This page may combine multiple inventors who share the name “COLOMBEAU BENJAMIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COLOMBEAU BENJAMIN

APPLIED MATERIALS INC

Forming non-line-of-sight source drain extension in an nMOS finFET using n-doped selective epitaxial growth

Horizontal gate all around and FinFET device isolation

Horizontal gate all around device isolation

Horizontal gate all around and FinFET device isolation

Integrated semiconductor processing

Horizontal gate all around device isolation

Horizontal gate all around and FinFET device isolation

Gate all-around device

Methods for GAA I/O formation by selective epi regrowth

Methods for GAA I/O formation by selective epi regrowth

Gate all around device with fully-depleted silicon-on-insulator

Doping techniques

Threshold voltage modulation for gate-all-around FET architecture

Gate all around I/O engineering

Gate interface engineering with doped layer

Gate all around I/O engineering

Doping techniques

Methods and apparatus for integrated selective monolayer doping

Integrated CMOS source drain formation with advanced control

Diffusion barrier layer

Selective silicon etch for gate all around transistors

Selective silicon etch for gate all around transistors

Cap oxidation for FinFET formation

Gate all-around device

Stress incorporation in semiconductor devices

Horizontal GAA nano-wire and nano-slab transistors

Horizontal GAA nano-wire and nano-slab transistors

Template for nanosheet source drain formation with bottom dielectric

Gate-all-around transistors and methods of forming

Gate all around backside power rail formation with backside dielectric isolation scheme

Treatments to improve device performance

Forming non-line-of-sight source drain extension in an NMOS FINFET using n-doped selective epitaxial growth

Integrated flowable low-k gap-fill and plasma treatment

Conformal oxidation for gate all around nanosheet I/O device

Void-free contact trench fill in gate-all-around FET architecture

Formation of gate all around device

VARIAN SEMICONDUCTOR EQUIPMENT ASS INC

Method for fabricating asymmetrical three dimensional device

Method for improving fin isolation

Method for fabricating three dimensional device

VARIAN SEMICONDUCTOR EQUIPMENT

Method of reducing contact resistance

Optimized halo or pocket cold implants

Technique for selectively processing three dimensional device

GLOBALFOUNDRIES SG PTE LTD

Method for fabricating semiconductor devices with reduced junction diffusion

Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction

UNIV SINGAPORE

Method for fabricating semiconductor devices with reduced junction diffusion

BILOIU COSTEL

Gallium ION source and materials therefore

PRADHAN NILAY ANIL

FinFET device fabrication using thermal implantation

APPLIED MATERIALS ISRAEL LTD

Imaging of crystalline defects

HATEM CHRISTOPHER R

Low temperature ion implantation

TAN DEXTER XUEMING

Method for fabricating semiconductor devices with shallow diffusion regions