Inventor

CASSIDY ANDREW S

US70 patents

⚠️ This page may combine multiple inventors who share the name “CASSIDY ANDREW S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CASSIDY ANDREW S

IBM

Massively parallel neural inference computing elements

Consolidating multiple neurosynaptic cores into one memory

Hardware architecture for simulating a neural network of neurons

Faulty core recovery mechanisms for a three-dimensional network on a processor array

Short-term memory using neuromorphic hardware

Yield tolerance in a neurosynaptic system

Scaling multi-core neurosynaptic networks across chip boundaries

Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

Self-timed, event-driven neurosynaptic core controller

Array of processor core circuits with reversible tiers

Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs

Hardware architecture for simulating a neural network of neurons

Mapping neural dynamics of a neural model on to a coarsely grained look-up table

Final faulty core recovery mechanisms for a two-dimensional network on a processor array

Dual deterministic and stochastic neurosynaptic core circuit

Dual deterministic and stochastic neurosynaptic core circuit

Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit

Runtime reconfigurable neural network processor core

Performing error detection during deterministic program execution

Scaling multi-core neurosynaptic networks across chip boundaries

Multiplexing physical neurons to optimize power and area

Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation

Yield tolerance in a neurosynaptic system

Peripheral device interconnections for neurosynaptic systems

Hardware architecture for simulating a neural network of neurons

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine

Memory-mapped interface for message passing computing systems

Flexible precision neural inference processing unit

Hardware architecture for simulating a neural network of neurons

Yield tolerance in a neurosynaptic system

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

Mapping neural dynamics of a neural model on to a coarsely grained look-up table

Data representation for dynamic precision in neural network cores

Networks for distributing parameters and data to neural network compute cores

Runtime reconfigurable neural network processor core

Instruction distribution in an array of neural network cores

Data distribution in an array of neural network cores

Massively parallel neural inference computing elements

Peripheral device interconnections for neurosynaptic systems

Dual deterministic and stochastic neurosynaptic core circuit

Converting digital numeric data to spike event data

Neural network weight distribution from a grid of memory elements

Low energy deep-learning networks for generating auditory features for audio processing pipelines

Hierarchical parallelism in a network of distributed neural network cores

ALCAREZ-ICAZA RIVERA RODRIGO

Multiplexing physical neurons to optimize power and area

ALVAREZ-ICAZA RIVERA RODRIGO

Globally asynchronous and locally synchronous (GALS) neuromorphic network