Consolidating multiple neurosynaptic cores into one memory

Abstract

Embodiments of the invention relate to a neural network system comprising a single memory block for multiple neurosynaptic core modules. One embodiment comprises a neural network system including a memory array that maintains information for multiple neurosynaptic core modules. Each neurosynaptic core module comprises multiple neurons. The neural network system further comprises at least one logic circuit. Each logic circuit receives neuronal firing events targeting a neurosynaptic core module of the neural network system, and said logic circuit integrates the firing events received based on information maintained in said memory for said neurosynaptic core module.

What is claimed is: 
     
       1. A neural network system, comprising:
 a memory array that maintains information for multiple neurosynaptic core modules, wherein each neurosynaptic core module comprises multiple neurons; and 
 at least one logic circuit, wherein each logic circuit:
 receives neuronal firing events targeting a neurosynaptic core module of the neural network system; and 
 integrates the firing events received based on information maintained in said memory array for said neurosynaptic core module. 
 
 
     
     
       2. The neural network system of  claim 1 , wherein:
 said memory array is organized into multiple subsets, wherein each subset corresponds to a neurosynaptic core module of the neural network system; and 
 each subset maintains neuronal attributes for neurons of a corresponding neurosynaptic core module. 
 
     
     
       3. The neural network system of  claim 2 , wherein:
 each subset is divided into multiple entries, wherein each entry maintains neuronal attributes for a corresponding neuron; and 
 for each entry, the neuronal attributes maintained in said entry includes synaptic connectivity information, neuron parameters, and routing data information for a corresponding neuron. 
 
     
     
       4. The neural network system of  claim 3 , wherein:
 each logic circuit corresponds to one or more neurosynaptic core modules of the neural network system. 
 
     
     
       5. The neural network system of  claim 4 , wherein:
 for each logic circuit that corresponds to one or more neurosynaptic core modules of the neural network system, said logic circuit:
 receives incoming neuronal firing events targeting a neuron of said one or more neurosynaptic core modules; 
 retrieves neuron attributes for said neuron from a corresponding entry of said memory array; 
 integrates the firing events received based on the neuron attributes for said neuron; 
 generates an outgoing neuronal firing event when the integrated firing events exceed a threshold neuron parameter for said neuron; and 
 updates at least one neuron attribute for said neuron. 
 
 
     
     
       6. The neural network system of  claim 5 , wherein:
 each logic circuit multiplexes computation and control logic for at least two neurosynaptic core modules. 
 
     
     
       7. The neural network system of  claim 6 , wherein:
 said memory array has multiple rows; and 
 each row includes at least one entry. 
 
     
     
       8. The neural network system of  claim 7 , wherein:
 each row maintains neuronal attributes for neurons of different neurosynaptic core modules. 
 
     
     
       9. The neural network system of  claim 7 , wherein:
 for each time step, said rows are read out sequentially. 
 
     
     
       10. The neural network system of  claim 9 , wherein:
 said memory array is scaled in width. 
 
     
     
       11. The neural network system of  claim 9 , wherein:
 said memory array is scaled in height. 
 
     
     
       12. A method, comprising:
 maintaining information for multiple neurosynaptic core modules in a memory array, wherein each neurosynaptic core module comprises multiple neurons; and 
 controlling said neurosynaptic core modules using at least one logic circuit, wherein each logic circuit receives neuronal firing events targeting a neurosynaptic core module, and said logic circuit integrates the firing events received based on information maintained in said memory array for said neurosynaptic core module. 
 
     
     
       13. The method of  claim 12 , further comprising:
 organizing said memory array into multiple subsets; 
 wherein each subset corresponds to a neurosynaptic core module; and 
 wherein each subset maintains neuronal attributes for neurons of a corresponding neurosynaptic core module. 
 
     
     
       14. The method of  claim 13 , further comprising:
 dividing each subset into multiple entries, wherein each entry maintains neuronal attributes for a corresponding neuron; 
 wherein, for each entry, the neuronal attributes maintained in said entry includes synaptic connectivity information, neuron parameters, and routing data information for a corresponding neuron. 
 
     
     
       15. The method of  claim 14 , further comprising:
 each logic circuit controlling one or more neurosynaptic core modules. 
 
     
     
       16. The method of  claim 15 , further comprising:
 for each logic circuit controlling one or more neurosynaptic core modules, said logic circuit:
 receiving incoming neuronal firing events targeting a neuron of said one or more neurosynaptic core modules; 
 retrieving neuron attributes for said neuron from a corresponding entry of said memory array; 
 integrating the firing events received based on the neuron attributes for said neuron; 
 generating an outgoing neuronal firing event when the integrated firing events exceed a threshold neuron parameter for said neuron; and 
 updating at least one neuron attribute for said neuron. 
 
 
     
     
       17. The method of  claim 16 , further comprising:
 for each logic circuit, multiplexing computation and control logic for at least two neurosynaptic core modules. 
 
     
     
       18. The method of  claim 17 , further comprising:
 scaling said memory array in width. 
 
     
     
       19. The method of  claim 17 , further comprising:
 scaling said memory array in height. 
 
     
     
       20. A non-transitory computer program product for a neural network system comprising multiple neurosynaptic core modules, the computer program product comprising a computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to:
 maintain information for said neurosynaptic core modules in a memory array, wherein each neurosynaptic core module comprises multiple neurons; and 
 control said neurosynaptic core modules using at least one logic circuit, wherein each logic circuit receives neuronal firing events targeting a neurosynaptic core module of the neural network system, and said logic circuit integrates the firing events received based on information maintained in said memory array for said neurosynaptic core module. 
 
     
     
       21. The program code of  claim 20 , further executable by the computer to:
 organize said memory array into multiple subsets; 
 wherein each subset corresponds to a neurosynaptic core module; and 
 wherein each subset maintains neuronal attributes for neurons of a corresponding neurosynaptic core module. 
 
     
     
       22. The program code of  claim 21 , further executable by the computer to:
 divide each subset into multiple entries, wherein each entry maintains neuronal attributes for a corresponding neuron; 
 wherein, for each entry, the neuronal attributes maintained in said entry includes synaptic connectivity information, neuron parameters, and routing data information for a corresponding neuron. 
 
     
     
       23. The program code of  claim 22 , further executable by the computer to:
 for each logic circuit, control one or more neurosynaptic core modules of the neural network system. 
 
     
     
       24. The program code of  claim 23 , further executable by the computer to:
 for each logic circuit, multiplex computation and control logic for at least two neurosynaptic core modules. 
 
     
     
       25. The program code of  claim 24 , further executable by the computer to:
 for each time step, read out each entry of each subset sequentially.