Inventor

ALVAREZ-ICAZA RIVERA RODRIGO

US39 patents

⚠️ This page may combine multiple inventors who share the name “ALVAREZ-ICAZA RIVERA RODRIGO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ALVAREZ-ICAZA RIVERA RODRIGO

IBM

Consolidating multiple neurosynaptic cores into one memory

Hardware architecture for simulating a neural network of neurons

Faulty core recovery mechanisms for a three-dimensional network on a processor array

Yield tolerance in a neurosynaptic system

Scaling multi-core neurosynaptic networks across chip boundaries

Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

Self-timed, event-driven neurosynaptic core controller

Array of processor core circuits with reversible tiers

Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs

Hardware architecture for simulating a neural network of neurons

Mapping neural dynamics of a neural model on to a coarsely grained look-up table

Final faulty core recovery mechanisms for a two-dimensional network on a processor array

Scaling multi-core neurosynaptic networks across chip boundaries

Multiplexing physical neurons to optimize power and area

Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation

Yield tolerance in a neurosynaptic system

Peripheral device interconnections for neurosynaptic systems

Hardware architecture for simulating a neural network of neurons

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Hardware architecture for simulating a neural network of neurons

Yield tolerance in a neurosynaptic system

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

Mapping neural dynamics of a neural model on to a coarsely grained look-up table

Peripheral device interconnections for neurosynaptic systems

Converting digital numeric data to spike event data

Globally asynchronous and locally synchronous (GALS) neuromorphic network

Converting spike event data to digital numeric data

Mapping neural dynamics of a neural model on to a coarsely grained look-up table

Faulty core recovery mechanisms for a three-dimensional network on a processor array

Neuromorphic network comprising asynchronous routers and synchronous core circuits

Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputs

Array of processor core circuits with reversible tiers

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

Faulty core recovery mechanisms for a three-dimensional network on a processor array

SMARTMOTION TECHNOLOGIES INC

Dielectric elastomer fiber transducers

ALVAREZ-ICAZA RIVERA RODRIGO

Globally asynchronous and locally synchronous (GALS) neuromorphic network