Inventor

MEROLLA PAUL A

US74 patents

⚠️ This page may combine multiple inventors who share the name “MEROLLA PAUL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MEROLLA PAUL A

IBM

Consolidating multiple neurosynaptic cores into one memory

Hardware architecture for simulating a neural network of neurons

Faulty core recovery mechanisms for a three-dimensional network on a processor array

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Implementing a neural network algorithm on a neurosynaptic substrate based on criteria related to the neurosynaptic substrate

Yield tolerance in a neurosynaptic system

Implementing a neural network algorithm on a neurosynaptic substrate based on metadata associated with the neural network algorithm

Scaling multi-core neurosynaptic networks across chip boundaries

Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuits

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Self-timed, event-driven neurosynaptic core controller

Array of processor core circuits with reversible tiers

Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Hardware architecture for simulating a neural network of neurons

Mapping neural dynamics of a neural model on to a coarsely grained look-up table

Final faulty core recovery mechanisms for a two-dimensional network on a processor array

Dual deterministic and stochastic neurosynaptic core circuit

Dual deterministic and stochastic neurosynaptic core circuit

Mapping of algorithms to neurosynaptic hardware

Scaling multi-core neurosynaptic networks across chip boundaries

Multiplexing physical neurons to optimize power and area

Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computation

Yield tolerance in a neurosynaptic system

Peripheral device interconnections for neurosynaptic systems

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Hardware architecture for simulating a neural network of neurons

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Mapping graphs onto core-based neuromorphic architectures

Neuromorphic event-driven neural computing architecture in a scalable neural network

Memory-mapped interface for message passing computing systems

Hardware architecture for simulating a neural network of neurons

Scalable neural hardware for the noisy-OR model of Bayesian networks

Yield tolerance in a neurosynaptic system

Providing transposable access to a synapse array using a recursive array layout

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

Mapping graphs onto core-based neuromorphic architectures

ARTHUR JOHN V

Low-power event-driven neural computing architecture in neural networks

Integrate and fire electronic neurons

Providing transposable access to a synapse array using a recursive array layout

Scalable neural hardware for the noisy-OR model of Bayesian networks

Providing transposable access to a synapse array using column aggregation

AKOPYAN FILIPP

Neuromorphic event-driven neural computing architecture in a scalable neural network

Neuromorphic event-driven neural computing architecture in a scalable neural network

ALCAREZ-ICAZA RIVERA RODRIGO

Multiplexing physical neurons to optimize power and area

ALVAREZ-ICAZA RIVERA RODRIGO

Globally asynchronous and locally synchronous (GALS) neuromorphic network

NEURALINK CORP

Brain-machine interface (BMI) with user interface (UI) aware controller