Inventor
BRAMBILLA CLAUDIO
IT12 patents
⚠️ This page may combine multiple inventors who share the name “BRAMBILLA CLAUDIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ST MICROELECTRONICS SRL
7 patentsUS6825523B2Nov 30, 2004
Process for manufacturing a dual charge storage location memory cell
ST MICROELECTRONICS SRL34 citations91
US6326266B1Dec 4, 2001
Method of manufacturing an EPROM memory device having memory cells organized in a tablecloth matrix
ST MICROELECTRONICS SRL7 citations71
US6251736B1Jun 26, 2001
Method for forming contactless MOS transistors and resulting devices, especially for use in non-volatile memory arrays
ST MICROELECTRONICS SRL7 citations67
US7115472B2Oct 3, 2006
Process for manufacturing a dual charge storage location memory cell
ST MICROELECTRONICS SRL2 citations61
US6365456B1Apr 2, 2002
Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground
ST MICROELECTRONICS SRL6 citations61
US6350671B1Feb 26, 2002
Method for autoaligning overlapped lines of a conductive material in integrated electronic circuits
ST MICROELECTRONICS SRL4 citations61
US6300195B1Oct 9, 2001
Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground
ST MICROELECTRONICS SRL5 citations57
SGS THOMSON MICROELECTRONICS
5 patentsUS5976933ANov 2, 1999
Process for manufacturing an integrated circuit comprising an array of memory cells
SGS THOMSON MICROELECTRONICS8 citations72
US6063663AMay 16, 2000
Method for manufacturing a native MOS P-channel transistor with a process for manufacturing non-volatile memories
SGS THOMSON MICROELECTRONICS12 citations71
US5894065AApr 13, 1999
Method for improving the intermediate dielectric profile, particularly for non-volatile memories
SGS THOMSON MICROELECTRONICS2 citations60
US6353243B1Mar 5, 2002
Process for manufacturing an integrated circuit comprising an array of memory cells
SGS THOMSON MICROELECTRONICS1 citations50
US6104058AAug 15, 2000
Method for improving the intermediate dielectric profile, particularly for non-volatile memories
SGS THOMSON MICROELECTRONICS0 citations49