Method for manufacturing a native MOS P-channel transistor with a process for manufacturing non-volatile memories

Abstract

A method is provided of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels having an interpoly dielectric layer sandwiched between the two polysilicon levels. The method has the following steps: (1) masking and defining active areas of the discrete integrated devices; (2) masking and defining the first polysilicon level using a Poly1 mask; and (3) masking and defining an intermediate dielectric layer using a matrix mask. The length of the native threshold channel of the native transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer. A subsequent step of masking and defining the second polysilicon level provides for the use of a Poly2 mask which extends the active area of the transistor with a greater width than the previous mask in order to enable, by subsequent etching, the two polysilicon levels to overlap in self-alignment over the channel region.

We claim: 
     
       1. A method of manufacturing a P-channel native MOS transistor in a circuit integrated on a semiconductor which also includes a matrix of non-volatile memory cells of the floating gate type with two polysilicon levels and having an interpoly dielectric layer sandwiched between the two polysilicon levels, said method comprising the steps of: masking and defining active areas of the discrete integrated devices;   masking and defining the first polysilicon level using a Poly1 mask;   masking and defining an intermediate dielectric layer using a matrix mask:   wherein the length of the native threshold channel of said transistor is defined by means of the matrix mask and by etching away the interpoly dielectric layer, and that for a subsequent step of masking and defining the second polysilicon level, a Poly2 mask is used which extends the active area of the transistor with a greater width than the previous matrix mask to enable, as by subsequent etching, the two polysilicon levels to overlap in self-alignment over the channel region.   
     
     
       2. The method according to claim 1, wherein said matrix mask extends the channel area of the native transistor and is utilized for screening said channel area from a threshold adjust implant of other transistors outside the matrix area. 
     
     
       3. The method according to claim 1, further comprising an etching step for defining, centrally of the channel region, a stack structure formed by the Poly1 and Poly2 levels in mutual contact excepting at a central zone separated by a trapped portion of interpoly. 
     
     
       4. The method according to claim 3, further comprising a P -  implantation of the lightly doped drain type in the lateral zones of the channel region. 
     
     
       5. The method according to claim 3, further comprising the formation of spacers on opposite sides of the stack structure which rises centrally of the channel region. 
     
     
       6. The method according to claim 5, further comprising a P +  implantation in the lateral zones of the channel region, which zones, through being partly screened off by the spacers, enable junctions of the lightly doped drain type to be defined laterally of the channel region. 
     
     
       7. The method according to claim 1, wherein said first mask screens the channel region from a slight light voltage shift implantation.