Inventor · disambiguated record
Manlio Sergio Cereda
Also filed as: CEREDA MANLIO S · CEREDA MANLIO SERGIO
13 granted patents·113 citations·filing 1989–2004
91Inventor score
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13 records- 0184US6825523B2Process for manufacturing a dual charge storage location memory cellST MICROELECTRONICS SRL·Filed 2002·Granted Nov 30, 2004·34 cites·27 claims
- 0256US6365456B1Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual groundST MICROELECTRONICS SRL·Filed 2000·Granted Apr 2, 2002·6 cites·16 claims
- 0350US6063663AMethod for manufacturing a native MOS P-channel transistor with a process for manufacturing non-volatile memoriesSGS THOMSON MICROELECTRONICS·Filed 1998·Granted May 16, 2000·12 cites·7 claims
- 0449US6350671B1Method for autoaligning overlapped lines of a conductive material in integrated electronic circuitsST MICROELECTRONICS SRL·Filed 2000·Granted Feb 26, 2002·4 cites·11 claims
- 0546US5663080AProcess for manufacturing MOS-type integrated circuitsST MICROELECTRONICS SRL·Filed 1995·Granted Sep 2, 1997·14 cites·13 claims
- 0645US7115472B2Process for manufacturing a dual charge storage location memory cellST MICROELECTRONICS SRL·Filed 2004·Granted Oct 3, 2006·2 cites·20 claims
- 0740US5696399AProcess for manufacturing MOS-type integrated circuitsST MICROELECTRONICS SRL·Filed 1995·Granted Dec 9, 1997·10 cites·4 claims
- 0840US5091329AMethod for programming mos and cmos rom memoriesSGS THOMSON MICROELECTRONICS·Filed 1989·Granted Feb 25, 1992·10 cites·7 claims
- 0938US6027965AMethod of manufacturing an integrated circuit with MOS transistors having high breakdown voltages, and with precision resistorsST MICROELECTRONICS SRL·Filed 1998·Granted Feb 22, 2000·10 cites·19 claims
- 1038US5976933AProcess for manufacturing an integrated circuit comprising an array of memory cellsSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Nov 2, 1999·8 cites·29 claims
- 1130US5894065AMethod for improving the intermediate dielectric profile, particularly for non-volatile memoriesSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Apr 13, 1999·2 cites·5 claims
- 1229US6353243B1Process for manufacturing an integrated circuit comprising an array of memory cellsSGS THOMSON MICROELECTRONICS·Filed 1999·Granted Mar 5, 2002·1 cites·4 claims
- 1327US6104058AMethod for improving the intermediate dielectric profile, particularly for non-volatile memoriesSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Aug 15, 2000·0 cites·40 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →