Inventor
BENNETT JOSEPH A
US35 patents
⚠️ This page may combine multiple inventors who share the name “BENNETT JOSEPH A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
33 patentsUS6901461B2May 31, 2005
Hardware assisted ATA command queuing
INTEL CORP123 citations99
US6907510B2Jun 14, 2005
Mapping of interconnect configuration space
INTEL CORP79 citations97
US6157970ADec 5, 2000
Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number
INTEL CORP60 citations96
US6131127AOct 10, 2000
I/O transactions on a low pin count bus
INTEL CORP62 citations96
US6119189ASep 12, 2000
Bus master transactions on a low pin count bus
INTEL CORP65 citations96
US5991841ANov 23, 1999
Memory transactions on a low pin count bus
INTEL CORP68 citations96
US7036122B2Apr 25, 2006
Device virtualization and assignment of interconnect devices
INTEL CORP57 citations95
US6792494B2Sep 14, 2004
Apparatus and method for parallel and serial PCI hot plug signals
INTEL CORP44 citations94
US6978351B2Dec 20, 2005
Method and system to improve prefetching operations
INTEL CORP27 citations93
US7328300B2Feb 5, 2008
Method and system for keeping two independent busses coherent
INTEL CORP43 citations92
US7260661B2Aug 21, 2007
Processing replies to request packets in an advanced switching context
INTEL CORP22 citations92
US6968410B2Nov 22, 2005
Multi-threaded processing of system management interrupts
INTEL CORP21 citations92
US6697904B1Feb 24, 2004
Preventing starvation of agents on a bus bridge
INTEL CORP32 citations92
US6658520B1Dec 2, 2003
Method and system for keeping two independent busses coherent following a direct memory access
INTEL CORP33 citations92
US6510475B1Jan 21, 2003
Data fetching control mechanism and method for fetching optimized data for bus devices behind host bridge
INTEL CORP20 citations92
US6466998B1Oct 15, 2002
Interrupt routing mechanism for routing interrupts from peripheral bus to interrupt controller
INTEL CORP24 citations92
US6151654ANov 21, 2000
Method and apparatus for encoded DMA acknowledges
INTEL CORP25 citations92
US7886177B2Feb 8, 2011
Method and apparatus of collecting timer ticks
INTEL CORP8 citations84
US7409483B2Aug 5, 2008
Methods and apparatuses to provide message signaled interrupts to level-sensitive drivers
INTEL CORP10 citations84
US7107369B2Sep 12, 2006
Connecting storage devices to a processor-based device
INTEL CORP15 citations84
US7225326B2May 29, 2007
Hardware assisted ATA command queuing
INTEL CORP9 citations74
US6820141B2Nov 16, 2004
System and method of determining the source of a codec
INTEL CORP11 citations74
US5889968AMar 30, 1999
Method and apparatus for interlocking a broadcast message on a bus
INTEL CORP12 citations73
US7203785B2Apr 10, 2007
Apparatus and method for parallel and serial PCI hot plug signals
INTEL CORP7 citations71
US6868469B2Mar 15, 2005
Data bridge and bridging
INTEL CORP7 citations70
US7743194B2Jun 22, 2010
Driver transparent message signaled interrupts
INTEL CORP1 citations63
US7689745B2Mar 30, 2010
Mechanism for synchronizing controllers for enhanced platform power management
INTEL CORP3 citations63
US6973594B2Dec 6, 2005
Method and apparatus for disabling a computer system bus upon detection of a power fault
INTEL CORP4 citations63
US6810443B2Oct 26, 2004
Optical storage transfer performance
INTEL CORP3 citations63
US6170033B1Jan 2, 2001
Forwarding causes of non-maskable interrupts to the interrupt handler
INTEL CORP6 citations63
US7506093B2Mar 17, 2009
Apparatus and method for converting parallel and serial PCI hot plug signals
INTEL CORP2 citations60
US7130992B2Oct 31, 2006
Detecting insertion of removable media
INTEL CORP1 citations52
US10007589B2Jun 26, 2018
System and method for universal serial bus (USB) protocol debugging
INTEL CORP0 citations51