Inventor

ASAKURA MIKIO

JP102 patents

⚠️ This page may combine multiple inventors who share the name “ASAKURA MIKIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ASAKURA MIKIO

MITSUBISHI ELECTRIC CORP

Semiconductor memory device containing a cache and an operation method thereof

Semiconductor memory device having a refresh-cycle program circuit

Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof

Semiconductor memory device having hierarchical bit line structure

Semiconductor memory device for simple cache system

Semiconductor memory device and method of checking same for defect

Clock synchronous type semiconductor memory device that can switch word configuration

Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output

Semiconductor memory device that can carry out read disturb testing and burn-in testing reliably

Column selecting circuit in semiconductor memory device

Arrangement of power supply and data input/output pads in semiconductor memory device

Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output

Semiconductor memory device

Arrangement of power supply and data input/output pads in semiconductor memory device

Semiconductor memory device for simple cache system

Semiconductor memory device for simple cache system with selective coupling of bit line pairs

Semiconductor memory device having power line arranged in a meshed shape

Layout of a semiconductor memory device

Semiconductor device incorporating internal voltage down converting circuit

Semiconductor memory device with cache memory addressable by block within each column

Semiconductor memory device

Semiconductor memory device for simple cache system

Semiconductor integrated circuit comprising step-up voltage generation circuit

Semiconductor memory device having a circuit for fast operation

Semiconductor memory device allowing repair of a defective memory cell with a redundant circuit in a multibit test mode

Method of fabricating semiconductor device with a fuse portion

Semiconductor memory device

Semiconductor memory device having internal address converting function, whose test and layout are conducted easily

Semiconductor memory device including internal power supply circuit generating a plurality of internal power supply voltages at different levels

Semiconductor memory device having power line arranged in a meshed shape

Semiconductor device structured to be less susceptible to power supply noise

Semiconductor memory device and method of checking same for defect

Potential detecting circuit and semiconductor integrated circuit

Semiconductor memory device having hierarchical bit line arrangement

Hierarchical bit line arrangement in a semiconductor memory

Semiconductor memory device having hierarchical boosted power-line scheme

Semiconductor memory device having power line arranged in a meshed shape

Column selecting circuit in semiconductor memory device

Semiconductor memory device with a built-in cache memory and operating method thereof

Dynamic semiconductor memory device

Dynamic semiconductor memory device having reduced soft error rate

Cache memory system having error correcting circuit

Semiconductor devices having redundancy circuitry and operating method therefor

Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration

Clock synchronous type semiconductor memory device that can switch word configuration

Semiconductor memory device with IO compression test mode

Semiconductor device with well of different conductivity types

Test circuit for a semiconductor memory device and method for burn-in test

Semiconductor memory device and semiconductor device

MITSUBSHI DENKI KABUSHIKI KAIS

Semiconductor device with efficiently arranged pads