Inventor

LIANG MONG-SONG

TW209 patents

⚠️ This page may combine multiple inventors who share the name “LIANG MONG-SONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIANG MONG-SONG

TAIWAN SEMICONDUCTOR MFG

Pseudo silicon on insulator MOSFET device

Method of making monos flash memory for multi-level logic

Multi-level, split-gate, flash memory cell and method of manufacture thereof

MOS devices with partial stressor channel

Backside contacts for MOS devices

Method of forming a semiconductor device with multiple thickness gate dielectric layers

Pseudo silicon on insulator MOSFET device

Multi-level, split-gate, flash memory cell

Method of manufacture of vertical stacked gate flash memory device

Multi-level split- gate flash memory cell

Method of making raised-bitline contactless trenched flash memory cell

MOS devices with partial stressor channel

Method of barrier-less integration with copper alloy

Barrier-free copper interconnect

Vertical stacked gate flash memory device

Method of protecting a copper pad structure during a fuse opening procedure

Fabrication of MIM capacitor in copper damascene process

OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors

Method of making dual isolation regions for logic and embedded memory devices

Body contact for a MOSFET device fabricated in an SOI layer

Body contacted SOI MOSFET

Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors

Process for fabricating MOS memory devices, with a self-aligned contact structure, and MOS logic devices with salicide, both on a single semiconductor chip

Blending integrated circuit technology

Method for forming buried plug contacts on semiconductor integrated circuits

Method for fabricating a DRAM cell with a T shaped storage capacitor

Method of making a body contacted SOI MOSFET

Method of making a body contact for a MOSFET device fabricated in an SOI layer

Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron mosfets

Multiple tilted angle ion implantation MOSFET method

Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors

Method for fabricating a dual-gate dielectric module for memory with embedded logic technology

Process of making a polysilicon barrier layer in a self-aligned contact module

Integrating a first contact structure in a gate last process

Super anneal for process induced strain modulation

Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement

Adhesion of copper and etch stop layer for copper alloy

Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement

Method for forming a self-passivated copper interconnect structure

Process technology architecture of embedded DRAM

Selectively controllable gas feed zones for a plasma reactor

Methods to create high-k dielectric gate electrodes with backside cleaning

CMOS FET with P-well with P- type halo under drain and counterdoped N- halo under source region

Method to form copper interconnects

OTP (open trigger path) latchup scheme using triple and buried well for sub-quarter micron transistors

Structure for a double wall tub shaped capacitor

Method for forming a ultra-thin gate insulator layer

Process technology architecture of embedded DRAM

Dynamic threshold MOSFET using accumulated base BJT level shifter for low voltage sub-quarter micron transistor

ADVANCED MICRO DEVICES INC

Method of improving silicon dioxide