MOS devices with partial stressor channel

Abstract

A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.

1. A semiconductor structure comprising:
 a semiconductor substrate having a first lattice constant; 
 a gate dielectric on the semiconductor substrate; 
 a gate electrode on the gate dielectric; and 
 a stressor having at least a portion adjacent to the gate electrode and in the semiconductor substrate, wherein the stressor has a tilted sidewall on a side adjacent the gate electrode, the stressor comprising:
 a first stressor layer having a second lattice constant substantially different from the first lattice constant, the first stressor layer having a top surface lower than a bottom surface of the gate dielectric; and 
 a second stressor layer on the first stressor layer, wherein the second stressor layer has a third lattice constant substantially different from the first and the second lattice constants. 
 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein the stressor comprises a tip portion under the gate electrode. 
     
     
       3. The semiconductor structure of  claim 2 , wherein the tip portion of the stressor has a width of greater than about 10 percent of a width of the gate electrode. 
     
     
       4. The semiconductor structure of  claim 1 , wherein the stressor has an end point under a gate spacer, wherein the gate spacer is on a respective sidewall of the gate electrode. 
     
     
       5. The semiconductor structure of  claim 1 , wherein the tilted sidewall of the stressor has a tilt angle of greater than about 15 degrees from vertical. 
     
     
       6. The semiconductor structure of  claim 1 , wherein the gate dielectric, the gate electrode, and the stressor are portions of a MOS device, and a channel length of the MOS device is in a (1, 1, 0) direction of the semiconductor substrate. 
     
     
       7. The semiconductor structure of  claim 6 , wherein the tilted sidewall is substantially in a (1, 1, 1) direction of the semiconductor substrate. 
     
     
       8. The semiconductor structure of  claim 1 , wherein the first stressor layer is conformal, and wherein the first stressor layer has a germanium atomic percentage substantially greater than a germanium atomic percentage of the second stressor layer. 
     
     
       9. The semiconductor structure of  claim 1 , wherein the first stressor layer is non-conformal, and wherein the first stressor layer has a germanium atomic percentage substantially less than a germanium atomic percentage of the second stressor layer. 
     
     
       10. The semiconductor structure of  claim 1 , wherein the tilted sidewall is physically connected to a bottom surface of the stressor, and wherein the bottom surface is substantially flat. 
     
     
       11. A MOS device comprising:
 a semiconductor substrate; 
 a gate dielectric on the semiconductor substrate; 
 a gate electrode on the gate dielectric; 
 a gate spacer on a sidewall of the gate electrode; 
 a recess in the semiconductor substrate, the recess being below and adjacent to the gate electrode, wherein a sidewall of the recess is substantially straight and tilted; and 
 a stressor in the recess, wherein the stressor comprises a tip, at least a first portion of the tip being under the gate spacer, the stressor comprising a first stressor layer having a top surface lower than a bottom surface of the gate dielectric, wherein the first stressor layer comprises a first stressor material having a first lattice constant, the stressor further comprising a second stressor layer on the first stressor layer, wherein the second stressor layer comprises a second stressor material having a second lattice constant substantially different from the first lattice constant. 
 
     
     
       12. The MOS device of  claim 11 , wherein a channel length direction of the MOS device is in a (1, 1, 0) plane of the semiconductor substrate. 
     
     
       13. The MOS device of  claim 11 , wherein the sidewall of the recess has a tilt angle of greater than about 30 degrees from vertical. 
     
     
       14. The MOS device of  claim 11 , wherein the first stressor layer is conformal, and wherein the first stressor material has a germanium atomic percentage substantially greater than a germanium atomic percentage of the second stressor material. 
     
     
       15. The MOS device of  claim 11 , wherein the first stressor layer is non-conformal, and wherein the first stressor material has a germanium atomic percentage substantially less than a germanium atomic percentage of the second stressor material. 
     
     
       16. The MOS device of  claim 11 , wherein the second stressor layer has a silicided surface. 
     
     
       17. The MOS device of  claim 11 , wherein the tip includes a second portion under the gate dielectric. 
     
     
       18. The MOS device of  claim 17 , wherein the second portion of the tip under the gate dielectric has a width of greater than about 25 percent of a width of the gate electrode. 
     
     
       19. The MOS device of  claim 17 , wherein the second portion of the tip under the gate dielectric has a tip width and wherein a ratio of the tip width to a width of the gate electrode is selected using a desired stress in a channel region under the gate dielectric. 
     
     
       20. The MOS device of  claim 11 , wherein the tip ends at an interface between the gate dielectric and the gate spacer. 
     
     
       21. A semiconductor structure comprising:
 a semiconductor substrate; 
 a gate stack on the semiconductor substrate; 
 a gate spacer on a sidewall of the gate stack; 
 a lightly doped source or drain (LDD) region comprising a different material from the semiconductor substrate, wherein the LDD region has at least a portion underlying the gate spacer, and wherein the LDD region has a substantially straight tilted interface with the semiconductor substrate; and 
 a source/drain region adjacent the gate spacer, wherein the source/drain region and the LDD region comprise an element selected from the group consisting essentially of germanium and carbon, and wherein atomic percentages of the element in the LDD region and at least a portion of the source/drain region are different. 
 
     
     
       22. The semiconductor structure of  claim 21 , wherein the interface has a tilt angle of between about 15 degrees and about 75 degrees. 
     
     
       23. The semiconductor structure of  claim 21 , wherein the source/drain region comprises a first layer and a second layer, both the first layer and the second layer having a different lattice structure than the semiconductor substrate. 
     
     
       24. A MOS device comprising:
 a semiconductor substrate; 
 a gate dielectric on the semiconductor substrate; 
 a gate electrode on the gate dielectric; 
 a gate spacer on a sidewall of the gate electrode; 
 a first stressor in a recess below and proximate to the gate electrode, wherein the first stressor has a sidewall below the gate spacer, a portion of the sidewall being substantially straight and tilted, and wherein the first stressor comprises germanium of a first atomic percentage and has an upper surface lower than a bottom surface of the gate electrode; and 
 a second stressor in the recess, wherein the second stressor comprises germanium of a second atomic percentage, the second atomic percentage different from the first atomic percentage.