P

Inventor

SELL BERNHARD

DE93 patents
⚠️ This page may combine multiple inventors who share the name “SELL BERNHARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

32 patents
US7335959B2Feb 26, 2008

Device with stepped source/drain region profile

INTEL CORP92 citations97
US7732285B2Jun 8, 2010

Semiconductor device having self-aligned epitaxial source and drain extensions

INTEL CORP41 citations92
US7663192B2Feb 16, 2010

CMOS device and method of manufacturing same

INTEL CORP23 citations91
US7943469B2May 17, 2011

Multi-component strain-inducing semiconductor regions

INTEL CORP22 citations90
US11239238B2Feb 1, 2022

Thin film transistor based memory cells on both sides of a layer of logic devices

INTEL CORP13 citations85
US11164975B2Nov 2, 2021

Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

INTEL CORP5 citations84
US10651310B2May 12, 2020

Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

INTEL CORP5 citations84
US10319843B2Jun 11, 2019

Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

INTEL CORP6 citations84
US10297549B2May 21, 2019

Method of forming stacked trench contacts and structures formed thereby

INTEL CORP5 citations84
US9922930B2Mar 20, 2018

Method of forming stacked trench contacts and structures formed thereby

INTEL CORP5 citations84
US9559060B2Jan 31, 2017

Method of forming stacked trench contacts and structures formed thereby

INTEL CORP5 citations84
US9437546B2Sep 6, 2016

Method of forming stacked trench contacts and structures formed thereby

INTEL CORP5 citations84
US9252267B2Feb 2, 2016

Method of forming stacked trench contacts and structures formed thereby

INTEL CORP5 citations84
US7829943B2Nov 9, 2010

Low-k isolation spacers for conductive regions

INTEL CORP10 citations84
US7768074B2Aug 3, 2010

Dual salicide integration for salicide through trench contacts and structures formed thereby

INTEL CORP13 citations84
US7687364B2Mar 30, 2010

Low-k isolation spacers for conductive regions

INTEL CORP13 citations84
US12520519B2Jan 6, 2026

Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

INTEL CORP2 citations75
US7112859B2Sep 26, 2006

Stepped tip junction with spacer layer

INTEL CORP7 citations74
US12148734B2Nov 19, 2024

Transistors, memory cells, and arrangements thereof

INTEL CORP3 citations73
US12015087B2Jun 18, 2024

Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

INTEL CORP2 citations73
US11721630B2Aug 8, 2023

Method of forming stacked trench contacts and structures formed thereby

INTEL CORP2 citations73
US11462541B2Oct 4, 2022

Memory cells based on vertical thin-film transistors

INTEL CORP2 citations73
US11758711B2Sep 12, 2023

Thin-film transistor embedded dynamic random-access memory with shallow bitline

INTEL CORP2 citations72
US11393927B2Jul 19, 2022

Memory cells based on thin-film transistors

INTEL CORP2 citations72
US11329047B2May 10, 2022

Thin-film transistor embedded dynamic random-access memory with shallow bitline

INTEL CORP4 citations72
US11728335B2Aug 15, 2023

Buried channel structure integrated with non-planar structures

INTEL CORP2 citations70
US11121073B2Sep 14, 2021

Through plate interconnect for a vertical MIM capacitor

INTEL CORP2 citations70
US12238913B2Feb 25, 2025

Two transistor memory cell using stacked thin-film transistors

INTEL CORP1 citations64
US12142566B2Nov 12, 2024

Method of forming stacked trench contacts and structures formed thereby

INTEL CORP0 citations63
US11784257B2Oct 10, 2023

Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

INTEL CORP0 citations63
US11335639B2May 17, 2022

Method of forming stacked trench contacts and structures formed thereby

INTEL CORP0 citations63
US7943992B2May 17, 2011

Metal gate structures with recessed channel

INTEL CORP5 citations63

INFINEON TECHNOLOGIES AG

15 patents
US7041568B2May 9, 2006

Method for the production of a self-adjusted structure on a semiconductor wafer

INFINEON TECHNOLOGIES AG212 citations99
US6835417B2Dec 28, 2004

Method and device for depositing thin layers via ALD/CVD processes in combination with rapid thermal processes

INFINEON TECHNOLOGIES AG115 citations98
US6633061B2Oct 14, 2003

SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method

INFINEON TECHNOLOGIES AG21 citations92
US6620724B1Sep 16, 2003

Low resistivity deep trench fill for DRAM and EDRAM applications

INFINEON TECHNOLOGIES AG23 citations92
US6800898B2Oct 5, 2004

Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors

INFINEON TECHNOLOGIES AG23 citations89
US6627940B1Sep 30, 2003

Memory cell arrangement

INFINEON TECHNOLOGIES AG13 citations84
US6674113B2Jan 6, 2004

Trench capacitor and method for manufacturing the same

INFINEON TECHNOLOGIES AG9 citations74
US6600680B2Jul 29, 2003

Circuit configuration and method for determining a time constant of a storage capacitor of a memory cell in a semiconductor memory

INFINEON TECHNOLOGIES AG8 citations74
US6541334B2Apr 1, 2003

Integrated circuit configuration having at least one buried circuit element and an insulating layer, and a method of manufacturing the integrated circuit configuration

INFINEON TECHNOLOGIES AG8 citations74
US6525363B1Feb 25, 2003

Integrated circuit configuration with at least one capacitor and method for producing the same

INFINEON TECHNOLOGIES AG8 citations74
US6504200B2Jan 7, 2003

DRAM cell configuration and fabrication method

INFINEON TECHNOLOGIES AG11 citations74
US6774005B2Aug 10, 2004

Method for fabricating a metal carbide layer and method for fabricating a trench capacitor containing a metal carbide

INFINEON TECHNOLOGIES AG9 citations73
US7199414B2Apr 3, 2007

Stress-reduced layer system for use in storage capacitors

INFINEON TECHNOLOGIES AG3 citations63
US7009900B2Mar 7, 2006

Circuit arrangement for reading out, evaluating and reading in again a charge state into a memory cell

INFINEON TECHNOLOGIES AG5 citations63
US6916704B2Jul 12, 2005

Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor

INFINEON TECHNOLOGIES AG6 citations63

SELL BERNHARD

3 patents

Showing the top 50 of 93 patents by PatentIndex Score.