SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method

Abstract

In a SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method, a multilayer barrier layer with a potential barrier and a diffusion barrier is used to reliably prevent diffusion of impurities between element layers. This allows semiconductor circuits to be produced with smaller structure sizes and with a higher integration density.

We claim:  
     
       1. A semiconductor circuit, comprising: 
       a SOI substrate, including:  
       a first element layer,  
       at least one second element layer, and  
       at least one isolation layer located between said first element layer and said second element layer, said isolation layer including a diffusion barrier and a multilayer barrier layer with a potential barrier;  
       at least one first semiconductor element that is formed in said first element layer;  
       at least one second semiconductor element that is formed in said at least second element layer; and  
       a conductive diffusion barrier layer electrically connecting said first semiconductor element and said second semiconductor elements.  
     
     
       2. A DRAM memory cell, comprising: 
       a SOI substrate, including:  
       a first element layer,  
       at least one second element layer, and  
       at least one isolation layer located between said first element layer and said second element layer, said isolation layer including a diffusion barrier and a multilayer barrier layer with a potential barrier;  
       at least one first semiconductor element that is formed in said first element layer;  
       at least one second semiconductor element that is formed in said at least second element layer; and  
       a conductive diffusion barrier layer electrically connecting said first semiconductor element and said second semiconductor elements;  
       said first semiconductor element including a selection transistor; and  
       said second semiconductor element including a trench capacitor.  
     
     
       3. The semiconductor circuit according to  claim 1  wherein: 
       the semiconductor circuit is a DRAM memory cell;  
       said first semiconductor element includes a selection transistor; and  
       said second semiconductor element includes a trench capacitor.  
     
     
       4. The semiconductor circuit according to  claim 1 , wherein said multilayer barrier layer includes a plurality of different isolation layers. 
     
     
       5. The semiconductor circuit according to  claim 4 , wherein said multilayer barrier layer includes a SiO 2 /Si 3 N 4 /SiO 2  layer sequence. 
     
     
       6. The semiconductor circuit according to  claim 1 , wherein said multilayer barrier layer includes at least one isolation layer and at least one conductive layer. 
     
     
       7. The semiconductor circuit according to  claim 6 , wherein said multilayer barrier layer includes at least one conductive layer including a material selected from the group consisting of Ti, TiSi, Ta, TaN, TiN, Pt, Ru, RuO, Ir, Mo, Ca, Ni, Hf, Zr, Ni—Si, MoN, HfN, MoSi, CoSi, TaSi, Au, Ag, Cu, Al, WSiN, C, Fe, W, WN and WSi x . 
     
     
       8. The semiconductor circuit according to  claim 1 , wherein said at least one second element layer includes a layer selected from the group consisting of an isolating layer, a semiconductive layer and a conductive layer. 
     
     
       9. The semiconductor circuit according to  claim 1 , wherein said multilayer barrier layer includes a thermal compensation layer.