Inventor

HU CHENMING

US166 patents

⚠️ This page may combine multiple inventors who share the name “HU CHENMING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HU CHENMING

TAIWAN SEMICONDUCTOR MFG

Methods and structures for planar and multiple-gate transistors formed on SOI

Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

Doping of semiconductor fin devices

Strained-channel multiple-gate transistor

Semiconductor nano-rod devices

Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices

Method of forming a transistor with a strained channel

Semiconductor nano-wire devices and methods of fabrication

Strained channel complementary field-effect transistors

CMOS inverters configured using multiple-gate transistors

CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof

Method for dicing semiconductor wafers

Multiple-gate transistors formed on bulk substrates

Contacts to semiconductor fin devices

Suppression of MOSFET gate leakage current

Capacitor that includes high permittivity capacitor dielectric

Strained-channel transistor structure with lattice-mismatched zone

Strained silicon structure

Strained-channel transistor and methods of manufacture

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

CMOS SRAM cell configured using multiple-gate transistors

Multiple-gate transistors with improved gate control

High performance PD SOI tunneling-biased MOSFET

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Strained channel on insulator device

Strained channel complementary field-effect transistors and methods of manufacture

Strained channel transistor and methods of manufacture

Capacitor with enhanced performance and method of manufacture

UNIV CALIFORNIA

Dual work function CMOS gate technology based on metal interdiffusion

Method of separating films from bulk substrates by plasma immersion ion implantation

Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation

Capacitorless DRAM device on silicon-on-insulator substrate

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

Tunneling transistor suitable for low voltage operation

Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation

Electrically programmable memory device employing source side injection

Method of separation films from bulk substrates by plasma immersion ion implantation

Ferroelectric nonvolatile dynamic random access memory device

Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

ACTEL CORP

Antifuse structure suitable for VLSI application

Antifuse structure suitable for VLSI application

Electrically programmable antifuse

Electrically programmable antifuse having a metal to metal structure

Electrically programmable antifuse and fabrication processes

Low voltage programming antifuse and transistor breakdown method for making same

MONOLITHIC SYSTEM TECH INC

Pseudo-nonvolatile memory incorporating data refresh operation

WANG CHIH-HAO

High performance CMOS devices and methods for making same