Strained-channel transistor structure with lattice-mismatched zone

Abstract

A strained-channel transistor structure with lattice-mismatched zone and fabrication method thereof. The transistor structure includes a substrate having a strained channel region, comprising a first semiconductor material with a first natural lattice constant, in a surface, a gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer, and a source region and drain region oppositely adjacent to the strained channel region, with one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.

1. A strained-channel transistor structure with improved transport properties, comprising:
 a strained channel region comprising a first semiconductor material with a first natural lattice constant;  
 a gate dielectric layer overlying the strained channel region;  
 a gate electrode overlying the gate dielectric layer; and  
 a source region and drain region oppositely adjacent to the strained channel region, the source region comprising a source extension region and a deep source region, the drain region comprising a drain extension region and a deep drain region, one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant.  
 
     
     
       2. The transistor structure as claimed in  claim 1 , wherein the lattice-mismatched zone is about 10 to 1000 Å thick. 
     
     
       3. The transistor structure as claimed in  claim 1 , wherein the lattice-mismatched zone is about 300 to 1000 Å thick. 
     
     
       4. The transistor structure as claimed in  claim 1 , wherein the first semiconductor material comprises silicon. 
     
     
       5. The transistor structure as claimed in  claim 1 , wherein the second semiconductor material comprises silicon and germanium. 
     
     
       6. The transistor structure as claimed in  claim 1 , wherein the second semiconductor material comprises silicon and carbon. 
     
     
       7. The transistor structure as claimed in  claim 5 , wherein molar fraction of germanium in the second semiconductor material is about 0.1 to 0.9. 
     
     
       8. The transistor structure as claimed in  claim 6 , wherein molar fraction of carbon in the second semiconductor material is about 0.01 to 0.04. 
     
     
       9. The transistor structure as claimed in  claim 6 , wherein the second semiconductor material further comprises germanium whose molar fraction in the second semiconductor material is less than ten times that of carbon in the second semiconductor material. 
     
     
       10. The transistor structure as claimed in  claim 1 , wherein the strained channel region is under a tensile strain in a source-to-drain direction. 
     
     
       11. The transistor structure as claimed in  claim 10 , wherein the tensile strain is about 0.1% to 4%. 
     
     
       12. The transistor structure as claimed in  claim 1 , wherein the strained channel region is under a compressive strain in a vertical direction. 
     
     
       13. The transistor structure as claimed in  claim 11 , wherein the compressive strain is about 0.1% to 4%. 
     
     
       14. The transistor structure as claimed in  claim 1 , wherein the strained channel region is under a compressive strain in a source-to-drain direction. 
     
     
       15. The transistor structure as claimed in  claim 14 , wherein the compressive strain is about 0.1% to 4%. 
     
     
       16. The transistor structure as claimed in  claim 1 , wherein the strained channel region is under a tensile strain in a vertical direction. 
     
     
       17. The transistor structure as claimed in  claim 16 , wherein the tensile strain is about 0.1% to 4%. 
     
     
       18. The transistor structure as claimed in  claim 1 , further comprising a cap layer on the lattice-mismatched zone. 
     
     
       19. The transistor structure as claimed in  claim 18 , wherein the cap layer comprises the first semiconductor material. 
     
     
       20. The transistor structure as claimed in  claim 1 , wherein the lattice-mismatched zone laterally extends into the source extension region and/or drain extension region. 
     
     
       21. The transistor structure as claimed in  claim 1 , wherein the gate dielectric layer is silicon oxide or silicon oxynitride. 
     
     
       22. The transistor structure as claimed in  claim 1 , wherein the gate dielectric layer is Al2O3, HfO2, ZrO2, HfON, HfSiO4, ZrSiO4, La2O3, or combinations thereof. 
     
     
       23. The transistor structure as claimed in  claim 22 , wherein the relative permittivity of the gate dielectric layer is larger than 5. 
     
     
       24. The transistor structure as claimed in  claim 1 , wherein the gate dielectric layer is about 3 to 100 Å thick. 
     
     
       25. The transistor structure as claimed in  claim 1 , wherein the gate electrode comprises poly-crystalline silicon. 
     
     
       26. The transistor structure as claimed in  claim 1 , wherein the gate electrode comprises poly-crystalline silicon germanium. 
     
     
       27. The transistor structure as claimed in  claim 1 , wherein the gate electrode comprises a metal. 
     
     
       28. The transistor structure as claimed in  claim 1 , wherein the gate electrode comprises a metal silicide. 
     
     
       29. The transistor structure as claimed in  claim 1 , further comprising a conductive material on the source region and drain region. 
     
     
       30. The transistor structure as claimed in  claim 29 , wherein the conductive material comprises a metal. 
     
     
       31. The transistor structure as claimed in  claim 29 , wherein the conductive material comprises a metal silicide. 
     
     
       32. A strained-channel transistor structure with improved transport properties, comprising:
 a strained channel region comprising a first semiconductor material with a first natural lattice constant;  
 a gate dielectric layer overlying the strained channel region;  
 a gate electrode overlying the gate dielectric layer; and  
 a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region comprising a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant different from the first natural lattice constant, wherein the lattice-mismatched zone further extends beyond the source region and/or drain region.