Inventor

YEO YEE-CHIA

TW392 patents

⚠️ This page may combine multiple inventors who share the name “YEO YEE-CHIA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YEO YEE-CHIA

TAIWAN SEMICONDUCTOR MFG

Methods and structures for planar and multiple-gate transistors formed on SOI

Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

Doping of semiconductor fin devices

Silicon-on-insulator chip with multiple crystal orientations

Semiconductor nano-rod devices

Strained-channel multiple-gate transistor

Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices

Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer

Method of forming a transistor with a strained channel

Semiconductor nano-wire devices and methods of fabrication

Strained channel complementary field-effect transistors

CMOS inverters configured using multiple-gate transistors

Multiple-gate transistors formed on bulk substrates

Contacts to semiconductor fin devices

Structure and method for forming the gate electrode in a multiple-gate transistor

Suppression of MOSFET gate leakage current

Capacitor that includes high permittivity capacitor dielectric

Strained-channel transistor structure with lattice-mismatched zone

Method of forming strained silicon on insulator substrate

Strained-channel transistor and methods of manufacture

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

CMOS SRAM cell configured using multiple-gate transistors

Multiple-gate transistors with improved gate control

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Dual fully-silicided gate MOSFETs

Silicon-on-insulator chip with multiple crystal orientations

Strained channel complementary field-effect transistors and methods of manufacture

Strained-channel semiconductor structure and method of fabricating the same

Strained channel transistor and methods of manufacture

Capacitor with enhanced performance and method of manufacture

Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

Silicide gate transistors and method of manufacture

Multiple-gate transistors formed on bulk substrates

Methods and structures for planar and multiple-gate transistors formed on SOI

Multiple-gate transistor structure

Gate electrode for a semiconductor fin device

Isolation spacer for thin SOI devices

TAIWAN SEMICONDUCTOR MFG CO LTD

Threshold voltage adjustment for a gate-all-around semiconductor structure

Strained nanowire CMOS device and method of forming

Multiple gate field-effect transistors having oxygen-scavenged gate stack

Multi-gate device and method of fabrication thereof

Semiconductor device structure with semiconductor wire

Conformal source and drain contacts for multi-gate field effect transistors

Replacement gate process for FinFET

Semiconductor Fin FET device with epitaxial source/drain

Semiconductor device and method of manufacturing the same

Method of manufacturing a semiconductor device and a semiconductor device

Metal liner overhang reduction and manufacturing method thereof

Reduction of Fin loss in the formation of FinFETS

Integrated circuit structure and method with solid phase diffusion