Inventor

LEE WEN-CHIN

TW102 patents

⚠️ This page may combine multiple inventors who share the name “LEE WEN-CHIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE WEN-CHIN

TAIWAN SEMICONDUCTOR MFG

Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

Tunnel field-effect transistors with superlattice channels

Strained channel complementary field-effect transistors

Strained-channel transistor structure with lattice-mismatched zone

Method of forming strained silicon on insulator substrate

Strained silicon structure

Strained-channel transistor and methods of manufacture

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

Strained channel on insulator device

Strained channel complementary field-effect transistors and methods of manufacture

Strained channel transistor and methods of manufacture

Isolation spacer for thin SOI devices

Diffusion topography engineering for high performance CMOS fabrication

CMOSFET with hybrid strained channels

Thin channel MOSFET with source/drain stressors

Isolation structure with nitrogen-containing liner and methods of manufacture

High performance semiconductor devices fabricated with strain-induced processes and methods for making same

Heterostructure resistor and method of forming the same

High performance CMOS with metal-gate and Schottky source/drain

Method for forming a device having multiple silicide types

Semiconductor device with high-k gate dielectric

Strained silicon layer semiconductor product employing strained insulator layer

BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture

Hybrid Schottky source-drain CMOS for high mobility and low barrier

Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

Epitaxy layer and method of forming the same

Strained silicon MOS devices

Transistor with a strained region and method of manufacture

Offset spacer formation for strained channel CMOS transistor

Semiconductor device substrate with embedded capacitor

Microelectronic device with depth adjustable sill

Strained channel on insulator device

Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions

CMOSFET with hybrid-strained channels

Method for forming a device having multiple silicide types

High performance semiconductor devices fabricated with strain-induced processes and methods for making same

Epitaxy layer and method of forming the same

SRAM cell having stepped boundary regions and methods of fabrication

Contact barrier structure and manufacturing methods

UNIV CALIFORNIA

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

UC LOGIC TECHNOLOGY CORP

Method and apparatus for detecting the position of a coordinate probe relative to a digitizing tablet

XU JEFF J

Metal gate transistor, integrated circuits, systems, and fabrication methods thereof

IND TECH RES INST

Optical waveguide structure

LAI LI-SHYUE

Multi-level flash memory cell capable of fast programming

KO CHIH-HSIN

CMOS devices with Schottky source and drain regions

FOXCONN ADVANCED TECH INC

Method for forming stacked via-holes in printed circuit boards

LEE WEN-CHIN

Forming chalcogenide semiconductor absorbers

LIN CHENG-HSIEN

Electromagnetic shielding composite and method for making the same

KUAN TA-MING

Methods for forming a transistor with a strained channel