CMOSFET with hybrid-strained channels

Abstract

Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.

1. A method of manufacturing a microelectronic device comprising:
 forming a silicon substrate with first and second wells of different dopant characteristics; 
 forming a first epitaxial silicon-germanium-carbon layer of a first formulation of silicon-germanium-carbon proximate to the first well; and 
 forming a second epitaxial silicon-germanium-carbon layer of a second formulation of silicon-germanium-carbon distinct from the first formulation proximate to the second well. 
 
   
   
     2. The method of  claim 1  wherein the first epitaxial silicon-germanium-carbon layer of a first formulation is formed directly on top of the first well. 
   
   
     3. The method of  claim 1  wherein the second epitaxial silicon-germanium-carbon layer of a second formulation is formed directly on top of the second well. 
   
   
     4. The method of  claim 1  further comprising:
 forming a hard mask over one of the wells. 
 
   
   
     5. A method of manufacturing a microelectronic device comprising:
 forming a silicon substrate with first and second wells of different dopant characteristics; 
 forming a first epitaxial silicon-germanium-carbon layer of a first formulation proximate to the first well; and 
 forming a second epitaxial silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well; 
 wherein a dopant characteristic in the first well is n-type and a dopant characteristic in the second well is p-type, and further comprising: 
 forming isolation regions in the top portion of the silicon substrate with a shallow trench process; 
 forming at least one hard mask over one of the wells thereby selectively forming the first epitaxial silicon-germanium-carbon layer wherein the formulation comprises more than twenty mol percent germanium over the first well and the second epitaxial silicon-germanium-carbon layer wherein the formulation comprises more than two mol percent carbon over the second well; 
 forming a silicon capping layer; 
 forming an insulator layer; and 
 forming a gate structure proximate to the first and second wells. 
 
   
   
     6. A method of manufacturing a microelectronic device sequentially comprising:
 forming a silicon substrate with first and second wells of different dopant characteristics; 
 forming an epitaxial layer of a first formulation of silicon-germanium-carbon over the first and second wells; 
 masking a first portion of the epitaxial layer overlying the first well; and 
 modifying a second portion of the epitaxial layer overlying the second well to a second formulation of silicon-germanium-carbon distinct from the first formulation.