Inventor

SINDALOVSKY VLADIMIR

US63 patents

⚠️ This page may combine multiple inventors who share the name “SINDALOVSKY VLADIMIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SINDALOVSKY VLADIMIR

AGERE SYSTEMS INC

On-chip debugger

Method and apparatus for generating status flags in a memory device

Variable frequency divider

Adaptive interference cancellation for ADSL

System for flexible memory paging in partitioning memory

Compensation techniques for reducing power consumption in digital circuitry

Phase interpolator having a phase jump

Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern

Method and apparatus for sigma-delta delay control in a delay-locked-loop

Serializer deserializer (SERDES) testing

Phase interpolator with output amplitude correction

Method and apparatus for controlling a clocked circuit having a register for storing a bit received from an input terminal and an output terminal connected to clock terminal of the clocked circuit

Method and apparatus for determining a position of an offset latch employed for decision-feedback equalization

Method and apparatus for automatic clock alignment

Parallel trimming method and apparatus for a voltage controlled delay loop

Statically controlled clock source generator for VCDL clock phase trimming

Multiple phase detection for delay loops

Trimming method and apparatus for voltage controlled delay loop with central interpolator

Data alignment method for arbitrary input with programmable content deskewing info

Method and apparatus for determining latch position for decision-feedback equalization using single-sided eye

Method and apparatus for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications

Parallel sampled multi-stage decimated digital loop filter for clock/data recovery

Voltage controlled delay loop with central interpolator

Pseudo asynchronous serializer deserializer (SERDES) testing

Symmetric signal distribution through abutment connection

Method and apparatus for adjusting a power supply of an integrated circuit

Method and apparatus for increased communication channel pre-emphasis for clock-like data patterns

Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system

Method and apparatus for generation of asynchronous clock for spread spectrum transmission

Methods and apparatus for spread spectrum generation using a voltage controlled delay loop

Alternating clock signal generation for delay loops

DC compensation method and apparatus

LSI CORP

Loss of lock detector for clock and data recovery system

Pattern-based loss of signal detector

SerDes data sampling gear shifter

Slicer trim methodolgy and device

IQ-skew adaptation for a symmetric eye in a SerDes receiver

LUCENT TECHNOLOGIES INC

Adaptive addressable circuit redundancy method and apparatus with broadcast write

System and method for testing of embedded processor

Adaptive addressable circuit redundancy method and apparatus

Memory bank organization correlating distance with a memory map

AGERE SYST GUARDIAN CORP

Memory aliasing method and apparatus

Dual clock D type flip-flop

SINDALOVSKY VLADIMIR

Pattern detector for serializer-deserializer adaptation

CDR with digitally controlled lock to reference

ABEL CHRISTOPHER J

Methods and apparatus for pseudo asynchronous testing of receive path in serializer/deserializer devices

Methods and apparatus for adaptation of continuous time-decision feedback equalizers with programmable adaptation patterns

MOBIN MOHAMMAD

Receiver training with cycle slip detection and correction

CHO JUNG HO

Alignment for multiple FIFO pointers

AZIZ PERVEZ M

Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system