Inventor

DIXON MARTIN G

US114 patents

⚠️ This page may combine multiple inventors who share the name “DIXON MARTIN G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DIXON MARTIN G

INTEL CORP

Flexible architecture and instruction for advanced encryption standard (AES)

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Method and apparatus for performing a shift and exclusive or operation in a single instruction

Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution

Rotate instructions that complete execution without reading carry flag

Add instructions to add three source operands

Method and apparatus to process SHA-2 secure hashing algorithm

Rotate instructions that complete execution either without writing or reading flags

Method and apparatus to process SHA-2 secure hashing algorithm

Method and apparatus for performing a shift and exclusive or operation in a single instruction

Method and apparatus to process SHA-2 secure hashing algorithm

Method and apparatus to process SHA-2 secure hashing algorithm

Method and apparatus for performing a shift and exclusive or operation in a single instruction

Instructions and logic to provide memory access key protection functionality

Processors, methods, and systems to relax synchronization of accesses to shared memory

Processors, methods, and systems to relax synchronization of accesses to shared memory

QoS based binary translation and application streaming

Addition instructions with independent carry chains

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

GOPAL VINODH

Matrix multiply accumulate instruction

SIMD integer multiply-accumulate instruction for multi-precision arithmetic

Method and apparatus for performing a shift and exclusive or operation in a single instruction

Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage

Add instructions to add three source operands

Rotate instructions that complete execution without reading carry flag

Addition instructions with independent carry chains

DIXON MARTIN G

Instruction for enabling a processor wait state

Controlling time stamp counter (TSC) offsets for mulitple cores and threads

System, method, and apparatus for a cache flush of a range of pages and TLB invalidation of a range of entries

YAP KIRK S

Method and apparatus to process KECCAK secure hashing algorithm

Method and apparatus to process SHA-2 secure hashing algorithm

GUERON SHAY

Flexible architecture and instruction for advanced encryption standard (AES)

RAJWAR RAVI

Transactional memory in out-of-order processors with XABORT having immediate argument

HUGHES CHRISTOPHER J

Gathering and scattering multiple data elements

HERBERT HOWARD C

Digital random number generator using partially entropic data

ZHAO LI

Monitoring cache usage in a distributed shared cache

COX GEORGE W

Method and apparatus for a non-deterministic random bit generator (NRBG)

WOLRICH GILBERT M

Instructions to perform Groestl hashing

CAPRIOLI PAUL

Instruction and logic to control transfer in a partial binary translation system