Inventor

VORBACH MARTIN

DE128 patents

⚠️ This page may combine multiple inventors who share the name “VORBACH MARTIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VORBACH MARTIN

PACT XPP TECHNOLOGIES AG

Runtime configurable arithmetic and logic cell

Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity

Runtime configurable arithmetic and logic cell

Method of repairing integrated circuits

Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)

Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)

I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures

Method for debugging reconfigurable architectures

Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells

Method for translating programs for reconfigurable architectures

Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)

Data processing system

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

Data processing system having integrated pipelined array data processor

Method for processing data

Logic cell array and bus system

Methods and devices for treating and processing data

Reconfigurable sequencer structure

Pipeline configuration unit protocols and communication

Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization

Reconfigurable sequencer structure

Methods and devices for treating and/or processing data

Method for debugging reconfigurable architectures

Method of self-synchronization of configurable elements of a programmable module

PACT GMBH

Method of self-synchronization of configurable elements of a programmable module

Method of self-synchronization of configurable elements of a programmable unit

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)

I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures

I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)

Method of the self-synchronization of configurable elements of a programmable unit

Run-time reconfiguration method for programmable units

Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity

VORBACH MARTIN

Optimization of loops and data flow sections in multi-core processor environment

Data processing method and device

Multi-core processing system

Method for the translation of programs for reconfigurable architectures

System and method for a cache in a multi-core processor

Data processing device and method

Reconfigurable elements

Device including a field having function cells and information providing cells controlled by the function cells

Hardware definition method including determining whether to implement a function as hardware or software

Method for debugging reconfigurable architectures

PACT INF TECH GMBH

Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--

Method for the automatic address generation of modules within clusters comprised of a plurality of these modules

PACT XPP TECH AG

Configurable logic integrated circuit having a multidimensional structure of configurable elements

Methods and systems for transferring data between a processing device and external devices

HYPERION CORE INC

Issuing instructions to multiple execution units