Optimization of loops and data flow sections in multi-core processor environment

Abstract

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

The invention claimed is: 
     
       1. A method for executing a program on a processor the method comprising:
 scheduling by a scheduler available processing hardware resources for executing at least one thread on at least one of a plurality of cores included in the processor, 
 each core having a multi-dimensional array of execution units and a register file, wherein the at least one thread is included in a plurality of threads partitioned from the program; 
 mapping the at least one thread for execution onto the hardware resources allocated by the scheduler; 
 configuring the interconnection between the execution units and the register file within one or more of the plurality of cores; and 
 creating one or more threads by the processor itself; 
 wherein creating one or more threads by the processor itself includes analyzing code by the processor. 
 
     
     
       2. The method of  claim 1 , wherein the scheduler is implemented in hardware. 
     
     
       3. The method of  claim 1 , wherein creating one or more threads by the processor itself includes detecting loops by the processor. 
     
     
       4. The method of  claim 1 , wherein creating one or more threads by the processor itself includes generating microcode for the one or more threads by the processor. 
     
     
       5. The method of  claim 4 , further comprising scheduling the one or more threads by the processor. 
     
     
       6. The method of  claim 1 , wherein the cores are Arithmetic Logic Unit (ALU) blocks. 
     
     
       7. The method of  claim 1 , wherein the one or more threads created by the processor include partitions of threads.