Assignee
VORBACH MARTIN
DE49 patents
Top patents by PatentIndex Score
US9043769B2May 26, 2015
Optimization of loops and data flow sections in multi-core processor environment
VORBACH MARTIN46 citations98
US8156284B2Apr 10, 2012
Data processing method and device
VORBACH MARTIN129 citations97
US7928763B2Apr 19, 2011
Multi-core processing system
VORBACH MARTIN27 citations96
US7996827B2Aug 9, 2011
Method for the translation of programs for reconfigurable architectures
VORBACH MARTIN46 citations94
US9086973B2Jul 21, 2015
System and method for a cache in a multi-core processor
VORBACH MARTIN27 citations93
US8812820B2Aug 19, 2014
Data processing device and method
VORBACH MARTIN50 citations93
US8686549B2Apr 1, 2014
Reconfigurable elements
VORBACH MARTIN23 citations93
US8429385B2Apr 23, 2013
Device including a field having function cells and information providing cells controlled by the function cells
VORBACH MARTIN10 citations93
US8250503B2Aug 21, 2012
Hardware definition method including determining whether to implement a function as hardware or software
VORBACH MARTIN22 citations93
US8069373B2Nov 29, 2011
Method for debugging reconfigurable architectures
VORBACH MARTIN10 citations93
US9152427B2Oct 6, 2015
Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file
VORBACH MARTIN25 citations92
US8914590B2Dec 16, 2014
Data processing method and device
VORBACH MARTIN26 citations92
US8230411B1Jul 24, 2012
Method for interleaving a program over a plurality of cells
VORBACH MARTIN16 citations92
US8099618B2Jan 17, 2012
Methods and devices for treating and processing data
VORBACH MARTIN16 citations92
US7844796B2Nov 30, 2010
Data processing device and method
VORBACH MARTIN23 citations92
US8869121B2Oct 21, 2014
Method for the translation of programs for reconfigurable architectures
VORBACH MARTIN17 citations91
US8058899B2Nov 15, 2011
Logic cell array and bus system
VORBACH MARTIN17 citations91
US8819505B2Aug 26, 2014
Data processor having disabled cores
VORBACH MARTIN12 citations86
US11061682B2Jul 13, 2021
Advanced processor architecture
VORBACH MARTIN6 citations84
US9348587B2May 24, 2016
Providing code sections for matrix of arithmetic logic units in a processor
VORBACH MARTIN9 citations84
US9037807B2May 19, 2015
Processor arrangement on a chip including data processing, memory, and interface elements
VORBACH MARTIN12 citations84
US8407525B2Mar 26, 2013
Method for debugging reconfigurable architectures
VORBACH MARTIN5 citations84
US8281108B2Oct 2, 2012
Reconfigurable general purpose processor having time restricted configurations
VORBACH MARTIN11 citations84
US7822881B2Oct 26, 2010
Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)
VORBACH MARTIN13 citations84
US8301872B2Oct 30, 2012
Pipeline configuration protocol and configuration unit communication
VORBACH MARTIN11 citations83
US8281265B2Oct 2, 2012
Method and device for processing data
VORBACH MARTIN14 citations83
US8726250B2May 13, 2014
Configurable logic integrated circuit having a multidimensional structure of configurable elements
VORBACH MARTIN5 citations82
US8312301B2Nov 13, 2012
Methods and devices for treating and processing data
VORBACH MARTIN4 citations74
US7822968B2Oct 26, 2010
Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs
VORBACH MARTIN4 citations74
US7782087B2Aug 24, 2010
Reconfigurable sequencer structure
VORBACH MARTIN4 citations74
US9703538B2Jul 11, 2017
Tool-level and hardware-level code optimization and respective hardware modification
VORBACH MARTIN3 citations73
US8686475B2Apr 1, 2014
Reconfigurable elements
VORBACH MARTIN5 citations73
US8471593B2Jun 25, 2013
Logic cell array and bus system
VORBACH MARTIN4 citations72
US8209653B2Jun 26, 2012
Router
VORBACH MARTIN5 citations70
US7840842B2Nov 23, 2010
Method for debugging reconfigurable architectures
VORBACH MARTIN2 citations63
US8468329B2Jun 18, 2013
Pipeline configuration protocol and configuration unit communication
VORBACH MARTIN1 citations62
US8145881B2Mar 27, 2012
Data processing device and method
VORBACH MARTIN5 citations62
US8127061B2Feb 28, 2012
Bus systems and reconfiguration methods
VORBACH MARTIN2 citations62
US10031888B2Jul 24, 2018
Parallel memory systems
VORBACH MARTIN1 citations52
US8312200B2Nov 13, 2012
Processor chip including a plurality of cache elements connected to a plurality of processor cores
VORBACH MARTIN0 citations52
US8310274B2Nov 13, 2012
Reconfigurable sequencer structure
VORBACH MARTIN0 citations52
US8195856B2Jun 5, 2012
I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures
VORBACH MARTIN0 citations52
US8156312B2Apr 10, 2012
Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units
VORBACH MARTIN0 citations52
US7899962B2Mar 1, 2011
I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
VORBACH MARTIN0 citations52
USRE44383EJul 16, 2013
Method of self-synchronization of configurable elements of a programmable module
VORBACH MARTIN0 citations45
USRE44365EJul 9, 2013
Method of self-synchronization of configurable elements of a programmable module
VORBACH MARTIN0 citations45
USRE45223EOct 28, 2014
Method of self-synchronization of configurable elements of a programmable module
VORBACH MARTIN0 citations42
USRE45109ESep 2, 2014
Method of self-synchronization of configurable elements of a programmable module
VORBACH MARTIN0 citations42
US9659221B2May 23, 2017
Video stream evaluation
VORBACH MARTIN1 citations41