Method of self-synchronization of configurable elements of a programmable module

Abstract

A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), and any configurable element can have access to a configuration register and a status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing a central synchronization instance.

What is claimed is: 
     
       1. A method for controlling data processing by an integrated circuit that includes a plurality of data processing elements that are arranged for at least one of arithmetically and logically processing data using a sequence of commands, the sequence including jumps, the method comprising:
 for each of a plurality of the processing elements that each include at least one corresponding register:
 predefining at least one corresponding configuration command; and 
 storing each of the at least one corresponding configuration command in one of the at least one register corresponding to the processing element; 
   processing data in at least one first processing element;   obtaining at least one of a comparison, a sign, a carryover, and an error state during the processing of the data in the at least one first processing element;   in response to the at least one of the comparison, the sign, the carry-over, and the error state, generating for the at least one second processing element at least one first synchronization signal within a data stream during runtime;   processing data in at least one second processing element in a stream-like manner; and   in response to the at least one first synchronization signal, selecting at least one particular command from the stored configuration commands in order to control a jump in the sequence.   
     
     
       2. A Field Programmable Gate Array (FPGA) integrated circuit comprising:
 an at least two dimensional configurable core structure including:   a plurality of components, a subset of which being configurable; and   a configurable interconnection system connecting the plurality of components;   wherein:
 at least one of the subset includes at least one cell that fulfills one of logic and arithmetic functions according to its respective configuration; 
 at least one of the subset of components includes a RAM; 
 at least one of the plurality of components includes a processor; 
 at least one of the subset of components includes an ALU; and 
 at least one of the subset of components is configurable at runtime by a configuration code provided by another of the subset of components, the configuration code representing one of a single function and a single interconnection. 
   
     
     
       3. The FPGA integrated circuit according to claim 2, wherein the configuration code is a result output from the at least one other of the subset of components, which output is connected via the configurable interconnection system to a configuration input of one of the subset of components that is configurable at runtime. 
     
     
       4. The FPGA integrated circuit according to claim 2, wherein the integrated circuit is one of a configurable arithmetic processor and a configurable arithmetic coprocessor. 
     
     
       5. The FPGA integrated circuit according to any one of claims 2 and 4, wherein each of at least some of the subset of components comprises at least one status information input from the configurable interconnection system. 
     
     
       6. The FPGA integrated circuit according to any one of claims 2 and 4, wherein at least some of the subset of components comprises at least one status information output to the configurable interconnection system. 
     
     
       7. The FPGA integrated circuit according to claim 6, wherein at least one of the at least some of the subset of components comprises at least one adder. 
     
     
       8. The FPGA integrated circuit according to claim 7, wherein the at least one adder includes an adder having a feed back channel for feeding back a result of the adder to an operand input of the adder via a multiplexer. 
     
     
       9. The FPGA integrated circuit according to claim 7, wherein at least some status information are generated by the at least one adder. 
     
     
       10. The FPGA integrated circuit according to claim 6, wherein each of the at least some of the subset of components comprises at least one comparator. 
     
     
       11. The FPGA integrated circuit according to claim 10, wherein at least some status information are generated by the at least one comparator. 
     
     
       12. The FPGA integrated circuit according to claim 6, wherein the at least some of the subset of components comprise at least one state-machine. 
     
     
       13. The FPGA integrated circuit according to claim 2, wherein the at least one component comprising the processor is configurable. 
     
     
       14. The FPGA integrated circuit according to claim 2, wherein the configuration code is generated at runtime as a processing result of the other of the subset of components.