Inventor · disambiguated record
Robert Münch
Also filed as: MUENCH ROBERT · MUENCH ROBERT M · MUENCH ROBERT MARKUS · MUNCH ROBERT
42 granted patents·3 pending applications·3,343 citations·filing 1995–2014
99Inventor score
Top patents by PatentIndex Score
45 records- 0199US7010667B2Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexityPACT XPP TECHNOLOGIES AG·Filed 2002·Granted Mar 7, 2006·280 cites·12 claims
- 0299US6697979B1Method of repairing integrated circuitsPACT XPP TECHNOLOGIES AG·Filed 2000·Granted Feb 24, 2004·261 cites·17 claims
- 0399US6477643B1Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)PACT GMBH·Filed 2000·Granted Nov 5, 2002·224 cites·11 claims
- 0499US6338106B1I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architecturesPACT GMBH·Filed 1999·Granted Jan 8, 2002·171 cites·18 claims
- 0598US7650448B2I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architecturesPACT XPP TECHNOLOGIES AG·Filed 2008·Granted Jan 19, 2010·81 cites·78 claims
- 0698US6513077B2I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architecturesPACT GMBH·Filed 2001·Granted Jan 28, 2003·124 cites·19 claims
- 0798US6425068B1Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)PACT GMBH·Filed 1997·Granted Jul 23, 2002·139 cites·25 claims
- 0897US7565525B2Runtime configurable arithmetic and logic cellPACT XPP TECHNOLOGIES AG·Filed 2004·Granted Jul 21, 2009·103 cites·19 claims
- 0997US6721830B2I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architecturesPACT XPP TECHNOLOGIES AG·Filed 2002·Granted Apr 13, 2004·77 cites·29 claims
- 1097US6687788B2Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)PACT XPP TECHNOLOGIES AG·Filed 2002·Granted Feb 3, 2004·147 cites·12 claims
- 1197US6526520B1Method of self-synchronization of configurable elements of a programmable unitPACT GMBH·Filed 2000·Granted Feb 25, 2003·123 cites·14 claims
- 1297US6119181AI/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architecturesPACT GMBH·Filed 1997·Granted Sep 12, 2000·159 cites·35 claims
- 1396US6405299B1Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexityPACT GMBH·Filed 1998·Granted Jun 11, 2002·122 cites·41 claims
- 1495US7237087B2Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cellsPACT XPP TECHNOLOGIES AG·Filed 2002·Granted Jun 26, 2007·69 cites·1 claims
- 1593US7028107B2Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like)PACT XPP TECHNOLOGIES AG·Filed 2002·Granted Apr 11, 2006·66 cites·27 claims
- 1693US6021490ARun-time reconfiguration method for programmable unitsPACT GMBH·Filed 1997·Granted Feb 1, 2000·182 cites·15 claims
- 1792US6542998B1Method of self-synchronization of configurable elements of a programmable modulePACT GMBH·Filed 1999·Granted Apr 1, 2003·121 cites·39 claims
- 1890US6480937B1Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--PACT INF TECH GMBH·Filed 1999·Granted Nov 12, 2002·142 cites·12 claims
- 1989US6728871B1Runtime configurable arithmetic and logic cellPACT XPP TECHNOLOGIES AG·Filed 1999·Granted Apr 27, 2004·95 cites·19 claims
- 2089US6081903AMethod of the self-synchronization of configurable elements of a programmable unitPACT GMBH·Filed 1997·Granted Jun 27, 2000·114 cites·16 claims
- 2189US5943242ADynamically reconfigurable data processing systemPACT GMBH·Filed 1995·Granted Aug 24, 1999·136 cites·23 claims
- 2288US8819505B2Data processor having disabled coresVORBACH MARTIN·Filed 2009·Granted Aug 26, 2014·12 cites·52 claims
- 2388US6571381B1Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)PACT XPP TECHNOLOGIES AG·Filed 1999·Granted May 27, 2003·114 cites·25 claims
- 2488US6088795AProcess for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)PACT GMBH·Filed 1997·Granted Jul 11, 2000·104 cites·49 claims
- 2586US7822881B2Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like)VORBACH MARTIN·Filed 2005·Granted Oct 26, 2010·13 cites·4 claims
- 2684US7036036B2Method of self-synchronization of configurable elements of a programmable modulePACT XPP TECHNOLOGIES AG·Filed 2003·Granted Apr 25, 2006·25 cites·1 claims
- 2781US6038650AMethod for the automatic address generation of modules within clusters comprised of a plurality of these modulesPACT INF TECH GMBH·Filed 1997·Granted Mar 14, 2000·102 cites·16 claims
- 2877US7822968B2Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputsVORBACH MARTIN·Filed 2009·Granted Oct 26, 2010·4 cites·138 claims
- 2971US6990555B2Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)PACT XPP TECHNOLOGIES AG·Filed 2004·Granted Jan 24, 2006·15 cites·1 claims
- 3065US7174443B1Run-time reconfiguration method for programmable unitsPACT XPP TECHNOLOGIES AG·Filed 2000·Granted Feb 6, 2007·9 cites·24 claims
- 3162US8914690B2Multi-core processor having disabled coresPACT XPP TECHNOLOGIES AG·Filed 2014·Granted Dec 16, 2014·1 cites·5 claims
- 3257US7243175B2I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architecturesPACT XPP TECHNOLOGIES AG·Filed 2004·Granted Jul 10, 2007·4 cites·2 claims
- 3356US2009153188A1PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)VORBACH MARTIN·Filed 2009·Application pending·0 cites
- 3455USRE44383EMethod of self-synchronization of configurable elements of a programmable moduleVORBACH MARTIN·Filed 2008·Granted Jul 16, 2013·0 cites·1 claims
- 3554US2009144485A1Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas, and the like)VORBACH MARTIN·Filed 2009·Application pending·0 cites
- 3653USRE45223EMethod of self-synchronization of configurable elements of a programmable moduleVORBACH MARTIN·Filed 2010·Granted Oct 28, 2014·0 cites·122 claims
- 3753USRE45109EMethod of self-synchronization of configurable elements of a programmable moduleVORBACH MARTIN·Filed 2010·Granted Sep 2, 2014·0 cites·14 claims
- 3853USRE44365EMethod of self-synchronization of configurable elements of a programmable moduleVORBACH MARTIN·Filed 2010·Granted Jul 9, 2013·0 cites·81 claims
- 3953US8156312B2Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control unitsVORBACH MARTIN·Filed 2007·Granted Apr 10, 2012·0 cites·62 claims
- 4052US2011010523A1Runtime configurable arithmetic and logic cellVORBACH MARTIN·Filed 2010·Application pending·0 cites
- 4151US7584390B2Method and system for alternating between programs for execution by cells of an integrated circuitPACT XPP TECHNOLOGIES AG·Filed 2004·Granted Sep 1, 2009·4 cites·26 claims
- 4246US7337249B2I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architecturesPACT XPP TECHNOLOGIES AG·Filed 2007·Granted Feb 26, 2008·0 cites·4 claims
- 4346US6968452B2Method of self-synchronization of configurable elements of a programmable unitPACT XPP TECHNOLOGIES AG·Filed 2003·Granted Nov 22, 2005·0 cites·7 claims
- 4445US8195856B2I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architecturesVORBACH MARTIN·Filed 2010·Granted Jun 5, 2012·0 cites·6 claims
- 4545US7899962B2I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architecturesVORBACH MARTIN·Filed 2009·Granted Mar 1, 2011·0 cites·42 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →