PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)

Abstract

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

1 . A field programmable gate array integrated circuit comprising:
 a high level configuration load unit; and   a plurality of cells configurable by the high level configuration load unit, at least some of the configurable cells being dynamically configurable at runtime by others of the configurable cells;   wherein at least one intermediate level configuration unit of the field programmable gate array integrated circuit is located between the high level configuration load unit and the at least some of the configurable cells, the at least one intermediate level configuration unit being adapted for configuring, dynamically at runtime, the at least some of the configurable cells.   
     
     
         2 . The field programmable gate array integrated circuit according to  claim 1 , wherein the field programmable gate array includes a memory arrangement for the at least one intermediate level configuration unit for receiving configuration strings from the high level configuration load unit. 
     
     
         3 . The field programmable gate array integrated circuit according to  claim 2 , wherein the intermediate level configuration unit comprises a controller for selecting from the memory arrangement a configuration string to be dynamically loaded into the at least some of the configurable cells. 
     
     
         4 . The field programmable gate array integrated circuit according to  claim 3 , wherein the controller is controlled by at least one event signal. 
     
     
         5 . The field programmable gate array integrated circuit according to  claim 3 , wherein the controller comprises at least one pointer into said memory arrangement for selecting from the memory arrangement a configuration string to be dynamically loaded into the at least some of the configurable cells. 
     
     
         6 . The field programmable gate array integrated circuit according to  claim 5 , wherein the pointer is controlled by at least one event signal. 
     
     
         7 . The field programmable gate array integrated circuit according to any one of  claims 4  and  6 , wherein at least one of the at least one event signal is generated by at least one of the configurable cells. 
     
     
         8 . The field programmable gate array integrated circuit according to any one of  claims 4  and  6 , wherein at least one of the at least one event signal is a clock signal. 
     
     
         9 . The field programmable gate array integrated circuit according to any one of  claims 1 ,  2 ,  3 , and  5 , wherein the intermediate level configuration unit dynamically configures a subset of the at least some of the configurable cells. 
     
     
         10 . The field programmable gate array integrated circuit according to any one of  claims 1 ,  2 ,  3 , and  5 , wherein the intermediate level configuration unit is hardwired into the field programmable gate array integrated circuit. 
     
     
         11 . The field programmable gate array integrated circuit according to any one of  claims 1 ,  2 ,  3 , and  5 , wherein the intermediate level configuration unit is configured into cells of the field programmable gate array integrated circuit. 
     
     
         12 . An intermediate level configuration unit for implementation in a field programmable gate array integrated circuit, wherein the intermediate level configuration unit is located between a high level configuration load unit and at least some of configurable cells that are dynamically configurable at runtime by other cells of the field programmable gate array integrated circuit, the intermediate level configuration unit comprising:
 memory for receiving configuration strings from the high level configuration load unit; and   a controller including at least one pointer into the memory for selecting from the memory a configuration string to be dynamically loaded into the at least some of the configurable cells.   
     
     
         13 . The intermediate level configuration unit according to  claim 12 , wherein each entry in said memory pointed to by said at least one pointer contains at least one configuration string for one of the configurable cells. 
     
     
         14 . The intermediate level configuration unit according to  claim 12 , wherein each entry in said memory pointed to by said at least one pointer contains at least one configuration string for a subset of the configurable cells. 
     
     
         15 . The intermediate level configuration unit according to any one of  claims 12 ,  13 , and  14 , wherein the controller is controlled by at least one event signal. 
     
     
         16 . The intermediate level configuration unit according to  claim 15 , wherein at least one of the at least one event signal is generated by at least one of the configurable cells. 
     
     
         17 . The intermediate level configuration unit according to  claim 15 , wherein at least one of the at least one event signal is a clock signal. 
     
     
         18 . The intermediate level configuration unit according to any one of  claims 12 ,  13 , and  14 , wherein the pointer is controlled by at least one event signal. 
     
     
         19 . The intermediate level configuration unit according to any one of  claims 12 ,  13 , and  14 , wherein the intermediate level configuration unit is hardwired into the field programmable gate array integrated circuit. 
     
     
         20 . The intermediate level configuration unit according to any one of  claims 12 ,  13 , and  14 , wherein the intermediate level configuration unit is configured into cells of the field programmable gate array integrated circuit. 
     
     
         21 . A field programmable gate array integrated circuit comprising:
 a high level configuration load unit; and   a plurality of configurable cells, at least some of the configurable cells being dynamically configurable at runtime by other cells of the plurality of configurable cells, and at least some of the configurable cells being adapted to operate as local memory cells.   
     
     
         22 . The field programmable gate array integrated circuit according to  claim 21 , wherein at least some of the local memory cells operate in a FIFO mode. 
     
     
         23 . The field programmable gate array integrated circuit according to  claim 21 , wherein at least some of the local memory cells are adapted for locally storing configuration strings for dynamically configuring the at least some of the configurable cells being dynamically configurable at runtime by other cells of the field programmable gate array. 
     
     
         24 . The field programmable gate array integrated circuit according to  claim 21 , wherein at least some of the local memory cells are adapted for at least one of transmitting data to and receiving data from the at least some of the configurable cells being dynamically configurable at runtime by other cells of the field programmable gate array. 
     
     
         25 . The field programmable gate array integrated circuit according to  claim 21 , wherein at least some of the local memory cells are adapted for simultaneously transmitting data to and receiving data from at least one of the configurable cells being dynamically configurable at runtime by other cells of the field programmable gate array. 
     
     
         26 . A runtime reconfigurable processing integrated circuit comprising:
 a plurality of cells configurable by a high level configuration load unit, at least some of the configurable cells being dynamically configurable at runtime by others of the configurable cells;   wherein at least one intermediate level configuration unit of the runtime reconfigurable processing integrated circuit is located between the high level configuration load unit and the at least some of the configurable cells, and is adapted for configuring the at least some of the configurable cells.   
     
     
         27 . The runtime reconfigurable processing integrated circuit according to  claim 26 , wherein a memory arrangement is provided for the at least one intermediate level configuration unit for receiving configuration strings from the high level configuration load unit. 
     
     
         28 . The runtime reconfigurable processing integrated circuit according to  claim 27 , wherein the intermediate level configuration unit comprises a controller for selecting from the memory arrangement a configuration string to be dynamically loaded into the at least some of the configurable cells. 
     
     
         29 . The runtime reconfigurable processing integrated circuit according to  claim 28 , wherein the controller comprises at least one pointer into said memory for selecting from the configuration memory a configuration string to be dynamically loaded into the at least some of the configurable cells. 
     
     
         30 . The runtime reconfigurable processing integrated circuit according to  claim 29 , wherein the pointer is controlled by at least one event signal. 
     
     
         31 . The runtime reconfigurable processing integrated circuit according to  claim 28 , wherein the controller is controlled by at least one event signal. 
     
     
         32 . The runtime reconfigurable processing integrated circuit according to any one of  claims 30  and  31 , wherein at least one of the at least one event signal is generated by at least one of the configurable cells. 
     
     
         33 . The runtime reconfigurable processing integrated circuit according to any one of  claims 30  and  31 , wherein at least one of the at least one event signal is a clock signal. 
     
     
         34 . The runtime reconfigurable processing integrated circuit according to any one of  claims 26 ,  27 ,  28 , and  29 , wherein the intermediate level configuration unit dynamically configures a subset of the at least some of the configurable cells. 
     
     
         35 . The runtime reconfigurable processing integrated circuit according to any one of  claims 26 ,  27 ,  28 , and  29 , wherein the at least one intermediate level configuration unit is hardwired into the runtime reconfigurable processing integrated circuit. 
     
     
         36 . The runtime reconfigurable processing integrated circuit according to any one of  claims 26 ,  27 ,  28 , and  29 , wherein the at least one intermediate level configuration unit is configured into cells of the runtime reconfigurable processing integrated circuit. 
     
     
         37 . An intermediate level configuration unit for implementation in a runtime reconfigurable processing integrated circuit, wherein the intermediate level configuration unit is located between a high level configuration load unit and at least some of configurable cells that are dynamically configurable at runtime by other cells of the runtime reconfigurable processing integrated circuit, the intermediate level configuration unit comprising:
 memory for receiving configuration strings from the high level configuration load unit; and   a controller including at least one pointer into the memory for selecting from the memory a configuration string to be dynamically loaded into the at least some of the configurable cells.   
     
     
         38 . The intermediate level configuration unit according to  claim 37 , wherein each entry in said memory pointed to by said pointer contains at least one configuration string for one of the configurable cells. 
     
     
         39 . The intermediate level configuration unit according to  claim 37 , wherein each entry in said memory pointed to by said pointer contains at least one configuration string for a subset of the configurable cells. 
     
     
         40 . The intermediate level configuration unit according to any one of  claims 37 ,  38 , and  39 , wherein the controller is controlled by at least one event signal. 
     
     
         41 . The intermediate level configuration unit according to  claim 40 , wherein at least one of the at least one event signal is generated by at least one of the configurable cells. 
     
     
         42 . The intermediate level configuration unit according to  claim 40 , wherein at least one of the at least one event signal is a clock signal. 
     
     
         43 . The intermediate level configuration unit according to any one of  claims 37 ,  38 , and  39 , wherein the pointer is controlled by at least one event signal. 
     
     
         44 . The intermediate level configuration unit according to any one of  claims 37 ,  38 , and  39 , wherein the intermediate level configuration unit is hardwired into the runtime reconfigurable processing integrated circuit. 
     
     
         45 . The intermediate level configuration unit according to any one of  claims 37 ,  38 , and  39 , wherein the intermediate level configuration unit is configured into cells of the runtime reconfigurable processing integrated circuit.