Inventor

DOUSKEY STEVEN M

US62 patents

⚠️ This page may combine multiple inventors who share the name “DOUSKEY STEVEN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DOUSKEY STEVEN M

IBM

Testing system interconnections using dynamic configuration and test generation

Shared channel masks in on-product test compression system

Test coverage of integrated circuits with test vector input spreading

Test coverage of integrated circuits with test vector input spreading

Test coverage of integrated circuits with masking pattern selection

Test coverage of integrated circuits with masking pattern selection

Adjusting latency in a scan cell

Chip testing with exclusive OR

Scan chain processing in a partially functional chip

Dynamic built-in self-test system

Method and apparatus for in-system redundant array repair on integrated circuits

Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system

Implementing enhanced diagnostics with intelligent pattern combination in automatic test pattern generation (ATPG)

Multi-core processor comparison encoding

Portion isolation architecture for chip isolation test

Managing chip testing data

Lowering power consumption during logic built-in self-testing (LBIST) via channel suppression

Implementing MISR compression methods for test time reduction

Self evaluation of system on a chip with multiple cores

Operating pulsed latches on a variable power supply

Method and apparatus for in-system redundant array repair on integrated circuits

Design structure for in-system redundant array repair in integrated circuits

Collecting diagnostic data from chips

Partitioned scan chain diagnostics using multiple bypass structures and injection points

Inserting bypass structures at tap points to reduce latch dependency during scan testing

Inserting bypass structures at tap points to reduce latch dependency during scan testing

Partitioned scan chain diagnostics using multiple bypass structures and injection points

Implementing enhanced scan chain diagnostics via bypass multiplexing structure

Implementing enhanced scan chain diagnostics via bypass multiplexing structure

Shared channel masks in on-product test compression system

Collecting diagnostic data from chips

Chip testing with exclusive OR

Hierarchal test block test pattern reduction in on-product test compression system

Hierarchal test block test pattern reduction in on-product test compression system

Logic built-in self-test channel skipping during functional scan operations

Scan chain processing in a partially functional chip

Managing redundancy repair using boundary scans

Managing redundancy repair using boundary scans

Self evaluation of system on a chip with multiple cores

Dynamic built-in self-test system

Operating pulsed latches on a variable power supply

Minimization of over-masking in an on product multiple input signature register (OPMISR)

Implementing over-masking removal in an on product multiple input signature register (OPMISR) test due to common channel mask scan registers (CMSR) loading

Implementing decreased scan data interdependence in on product multiple input signature register (OPMISR) through PRPG control rotation

Method and apparatus for in-system redundant array repair on integrated circuits

Minimization of over-masking in an on product multiple input signature register (OPMISR)

CADENCE DESIGN SYSTEMS INC

Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies

DOUSKEY STEVEN M

Dynamic scan

BELLOFATTO RALPH E

Testing and operating a multiprocessor chip with processor redundancy

GLOBALFOUNDRIES INC

Test coverage of integrated circuits with masking pattern selection