Inventor

AUGENDRE EMMANUEL

FR31 patents

⚠️ This page may combine multiple inventors who share the name “AUGENDRE EMMANUEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AUGENDRE EMMANUEL

COMMISSARIAT ENERGIE ATOMIQUE

Method for making a semiconductor device with nanowire and aligned external and internal spacers

Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor

Method for making a semiconductor device with a compressive stressed channel

Method for producing a semiconductor device with self-aligned internal spacers

Method for making a semiconductor device with self-aligned inner spacers

Method of producing a channel structure formed from a plurality of strained semiconductor bars

Method for fabricating a transistor having a vertical channel having nano layers

Process for fabricating a field effect transistor having a coating gate

Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers

Method for causing tensile strain in a semiconductor film

Manufacturing process of an RF-SOI trapping layer substrate resulting from a crystalline transformation of a buried layer

Electronic device including at least one nano-object

Method for fabricating a field-effect transistor

Transistor comprising a channel placed under shear strain and fabrication process

Transistor comprising a channel placed under shear strain and fabrication process

Semiconductor structure comprising a buried porous layer for RF applications

RF substrate structure and method of production

Method of manufacturing at least one field effect transistor having epitaxially grown electrodes

FinFET transistor comprising portions of SiGe with a crystal orientation [111]

Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions

Method for fabricating a field effect transistor having a surrounding grid

Process for fabricating a field effect transistor having a coating gate

Process for fabricating a vertical-channel nanolayer transistor

Method for producing a microelectronic device

Method for transferring a thin layer with supply of heat energy to a fragile zone via an inductive layer

Method of modifying the strain state of a semiconducting structure with stacked transistor channels

Method of fabricating a microelectronic structure of a semiconductor on insulator type with different patterns

AUGENDRE EMMANUEL

Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit

IMEC INTER UNI MICRO ELECTR

Semiconductor device with selectable gate thickness and method of manufacturing such devices

IBM

Optimizing junctions of gate all around structures with channel pull back

ANDRIEU FRANÇOIS

Method of adjusting the threshold voltage of a transistor by a buried trapping layer