RF substrate structure and method of production

Abstract

Producing a semiconductor or piezoelectric on-insulator type substrate for RF applications which is provided with a porous layer under the BOX layer and under a layer of polycrystalline semiconductor material.

The invention claimed is: 
     
       1. A structure provided with a substrate comprising a surface layer on or above which at least one RF circuit component, is formed or is to be formed, said surface layer being disposed on, and in contact with, an insulating layer, said insulating layer being disposed on, and in contact with, a pedestal, said pedestal comprising:
 a support layer of a given semiconductor material, 
 a trap-rich layer comprising a layer of polycrystalline semiconductor material located between said insulating layer and said support layer, said pedestal further comprising, between said support layer and said insulating layer: 
 a porous layer provided with a lower face in contact with said support layer, said porous layer being formed of a porous material with closed pores, the closed-pore porous material being composed of a solid skeleton and a distribution of closed pores, the closed pores being empty or filled with gas. 
 
     
     
       2. The structure according to  claim 1 , said layer of polycrystalline semiconductor material comprising an upper face in contact with said insulating layer, and a lower face opposite to said upper face, said lower face being in contact with said porous layer. 
     
     
       3. The structure according to  claim 2 , an upper portion of said solid skeleton of the porous layer being in contact with said lower face of said layer of polycrystalline semiconductor material and also being of polycrystalline semiconductor material. 
     
     
       4. The structure according to  claim 2 , wherein the solid skeleton of the porous layer is of single crystal semiconductor material, in particular integrally of single crystal semiconductor material, the porous layer and the layer of polycrystalline semiconductor material being superimposed. 
     
     
       5. The structure according to  claim 1 , the trap-rich layer and the porous layer being distinct layers, said solid skeleton being at least partially a single crystal skeleton. 
     
     
       6. The structure according to  claim 1 , a layer of amorphous semiconductor material being arranged between the trap-rich layer and the porous layer. 
     
     
       7. The structure according to  claim 1 , wherein said layer of polycrystalline semiconductor material and said porous layer are located facing a given region of said surface layer, another region of said surface layer juxtaposed to said given region being not located facing said layer of polycrystalline semiconductor material or said porous layer. 
     
     
       8. A microelectronic device comprising a structure according to  claim 1 , wherein said surface layer is a semiconducting layer, the device comprising:
 at least one transistor, said transistor having a channel region arranged in said surface semiconducting layer, and/or, 
 an RF component, in particular of the inductor or antenna type. 
 
     
     
       9. A method for manufacturing a structure according to  claim 1 , wherein the porous layer is made by porosifying a layer of given semiconductor material of said pedestal by implanting, in particular hydrogen or rare gas, implanting being followed by thermal annealing and/or laser treatment. 
     
     
       10. The method according to  claim 9 , wherein said implanting is performed so as to form a porous surface region on the surface of said pedestal. 
     
     
       11. The method according to  claim 9 , wherein producing the layer of polycrystalline semiconductor material comprises depositing a layer of amorphous semiconductor material onto the porous layer. 
     
     
       12. The method of  claim 9 , wherein producing the layer of polycrystalline semiconductor material comprises amorphisation implanting a region of said pedestal so as to form an amorphous region. 
     
     
       13. The method according to  claim 12  wherein said porous layer is formed by ion implantation so as to keep a non-porous surface region on the porous layer, said amorphisation implantation being performed so as to form the amorphous region in at least said surface region or at least said surface region and an upper part of said porous layer. 
     
     
       14. The method according to  claim 11 , wherein the method further comprises a recrystallisation step, by laser annealing and/or by thermal annealing with temperature and duration provided so as to transform said amorphous semiconducting layer or said amorphous region into said layer of polycrystalline material. 
     
     
       15. The method according to  claim 8 , wherein said porous layer and said layer of polycrystalline material are formed in a bulk substrate or of a bulk substrate covered with an insulating layer forming said pedestal, the method comprising a step of attaching a donor substrate onto said bulk substrate, said donor substrate comprising an insulating layer and a layer of piezoelectric or semiconductor material in which said surface layer is able to be formed. 
     
     
       16. The structure according to  claim 1 , wherein said solid skeleton is made of a semi-conductor material. 
     
     
       17. The structure according to  claim 1 , wherein said solid skeleton is made of said given semiconductor material.