Inventor

BEYER SVEN

DE84 patents

⚠️ This page may combine multiple inventors who share the name “BEYER SVEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BEYER SVEN

GLOBALFOUNDRIES INC

Programmable logic elements and methods of operating the same

Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure

Integrated circuit including a dummy gate structure and method for the formation thereof

Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure

Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material

Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material

Work function adjustment in high-k gate stacks for devices of different threshold voltage

Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer

Transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor

Ferro-FET device with buried buffer/ferroelectric layer stack

Superior fill conditions in a replacement gate approach by corner rounding prior to completely removing a placeholder material

BULEX contacts in advanced FDSOI techniques

Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure including a nonvolatile memory cell

Methods for forming integrated circuits that include a dummy gate structure

Maintaining integrity of a high-K gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy

Capacitor structure and method of forming a capacitor structure

Flash memory device

Flash memory device

Gate electrode with a shrink spacer

BEYER SVEN

Multiple gate transistor having homogenously silicided fin end portions

Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials

Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing

High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

Contacts and vias of a semiconductor device formed by a hard mask and double exposure

High-k metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning

Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors

SCHEIPER THILO

Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition

Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

Short channel transistor with reduced length variation by using amorphous electrode material during implantation

Contact bars with reduced fringing capacitance in a semiconductor device

Superior integrity of high-k metal gate stacks by capping STI regions

Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation

ADVANCED MICRO DEVICES INC

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same

Method of making a semiconductor device comprising isolation trenches inducing different types of strain

Methods for fabricating an integrated circuit

Structured strained substrate for forming strained transistors with reduced thickness of active layer

HOENTSCHEL JAN

Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers

Enhanced confinement of sensitive materials of a high-K metal gate electrode structure

High-K metal gate electrode structures formed at different process stages of a semiconductor device

Strain memorization in strained SOI substrates of semiconductor devices

GRIEBENOW UWE

Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch

Optical signal transfer in a semiconductor device by using monolithic opto-electronic components

CARTER RICHARD

Work function adjustment in a high-K gate electrode structure after transistor fabrication by using lanthanum

Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization

Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning

GLOBAL FOUNDRIES INC

Two step optical planarizing layer etch

ONESPIN SOLUTIONS GMBH

Equivalence verification between transaction level models and RTL at the example to processors

GLOBALFOUNDRIES US INC

Structure including a cross-bar router and method