Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure including a nonvolatile memory cell

Abstract

A method includes providing a semiconductor structure including a nonvolatile memory cell element and one or more electrically insulating layers covering the nonvolatile memory cell element. The nonvolatile memory cell element includes a source region, a channel region, a drain region and a floating gate over at least a first portion of the channel region. A first opening is formed in the electrically insulating layers over the floating gate, a control gate insulation layer is deposited, and a second opening is formed in the electrically insulating layers over the drain region. The first opening and the second opening are filled with an electrically conductive material. The electrically conductive material in the first opening provides a control gate of the nonvolatile memory cell element and the electrically conductive material in the second opening provides an electrical contact to the drain region.

What is claimed: 
     
       1. A method, comprising:
 providing a semiconductor structure comprising a nonvolatile memory cell element and one or more electrically insulating layers covering said nonvolatile memory cell element, said nonvolatile memory cell element comprising a source region, a channel region, a drain region and a floating gate over at least a first portion of said channel region; 
 forming a first opening in said one or more electrically insulating layers over said floating gate; 
 after the formation of said first opening, depositing a control gate insulation layer; 
 after the deposition of said control gate insulation layer, forming a second opening in said one or more electrically insulating layers over said drain region; and 
 filling said first opening and said second opening with an electrically conductive material, wherein said electrically conductive material in said first opening provides a control gate of said nonvolatile memory cell element and said electrically conductive material in said second opening provides an electrical contact to said drain region. 
 
     
     
       2. The method of  claim 1 , wherein said nonvolatile memory cell element further comprises a select gate, wherein at least a portion of said select gate is provided over a second portion of said channel region, wherein said first portion of said channel region is adjacent said source region, wherein said second portion of said channel region is between said first portion of said channel region and said drain region, wherein said floating gate is provided over said first portion of said channel region but not over said second portion of said channel region, and wherein the method further comprises:
 after the deposition of said control gate insulation layer, forming a third opening in said one or more electrically insulating layers over said select gate and filling said third opening with said electrically conductive material, wherein said electrically conductive material in said third opening provides an electrical contact to said select gate. 
 
     
     
       3. The method of  claim 2 , wherein said nonvolatile memory cell element further comprises an erase gate provided over said source region, and wherein the method further comprises:
 after the deposition of said control gate insulation layer, forming a fourth opening in said one or more electrically insulating layers over said erase gate and filling said fourth opening with said electrically conductive material, wherein said electrically conductive material in said fourth opening provides an electrical contact to said erase gate. 
 
     
     
       4. The method of  claim 3 , wherein said filling of said first opening, said second opening, said third opening and said fourth opening with said electrically conductive material comprises depositing a layer of said electrically conductive material over said semiconductor structure and performing a polishing process wherein portions of said electrically conductive material outside said first opening, said second opening, said third opening and said fourth opening are removed. 
     
     
       5. The method of  claim 4 , wherein said one or more electrically insulating layers comprise a liner layer over said nonvolatile memory cell and a layer of an interlayer dielectric over said liner layer, and wherein the formation of said first opening comprises:
 forming a first mask over said semiconductor structure; 
 performing a first etch process, said first etch process selectively removing a material of said interlayer dielectric relative to a material of said first mask and a material of said liner layer; 
 after said first etch process, performing a second etch process, said second etch process selectively removing said material of said liner layer relative to said material of said mask and said material of said interlayer dielectric; and 
 removing said first mask. 
 
     
     
       6. The method of  claim 5 , wherein said second etch process additionally removes a portion of said floating gate wherein at least one of a formation of a recess in said floating gate and a roughening of a surface of said floating gate are obtained. 
     
     
       7. The method of  claim 6 , wherein said nonvolatile memory cell further comprises a first sidewall spacer at a sidewall of said select gate and a second sidewall spacer at a sidewall of said erase gate, and wherein said second etch process selectively removes said material of said liner layer relative to a material of said first sidewall spacer and a material of said second sidewall spacer. 
     
     
       8. The method of  claim 7 , wherein the deposition of said control gate insulation layer comprises:
 depositing a first sublayer of said control gate insulation layer comprising silicon dioxide; 
 depositing a second sublayer of said control gate insulation layer comprising silicon nitride over said first sublayer of said control gate insulation layer; and 
 depositing a third sublayer of said control gate insulation layer comprising silicon dioxide over said second sublayer of said control gate insulation layer. 
 
     
     
       9. The method of  claim 8 , wherein the formation of said second opening, said third opening and said fourth opening comprises:
 forming a planarization layer over said semiconductor structure, said planarization layer filling said first opening and providing a planarization of said semiconductor structure; 
 forming a second mask over said planarization layer; 
 performing one or more etch processes adapted to remove materials of said control gate insulation layer, said layer of interlayer dielectric and said liner layer; and 
 removing said second mask and said planarization layer. 
 
     
     
       10. The method of  claim 9 , wherein said electrically conductive material comprises tungsten. 
     
     
       11. The method of  claim 10 , further comprising, before the deposition of said layer of said electrically conductive material, performing at least one of an atomic layer deposition process and a sputtering process, said at least one of said atomic layer deposition process and said sputter process depositing an adhesion layer comprising at least one of titanium nitride and tantalum nitride over said semiconductor structure.