Inventor

WANG CHENG C

US60 patents

⚠️ This page may combine multiple inventors who share the name “WANG CHENG C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG CHENG C

FLEX LOGIX TECH INC

Multiplexer-memory cell circuit, layout thereof and method of manufacturing same

Multiplier-accumulator circuitry, and processing pipeline including same

Multiplier-accumulator circuitry, and processing pipeline including same

Multiplier-accumulator circuit, logic tile architecture for multiply-accumulate, and IC including logic tile array

Test circuitry and techniques for logic tiles of FPGA

Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network

Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof

Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same

Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof

Clock architecture, including clock mesh fabric, for FPGA, and method of operating same

Clock distribution and generation architecture for logic tiles of an integrated circuit and method of operating same

Block memory layout and architecture for programmable logic IC, and method of operating same

Logarithmic addition-accumulator circuitry, processing pipeline including same, and methods of operation

IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory

MAC processing pipeline having conversion circuitry, and methods of operating same

IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory

FPGA having a virtual array of logic tiles, and method of configuring and operating same

Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network

Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same

Programmable decoupling capacitance of configurable logic circuitry and method of operating same

Multiplexer-memory cell circuit, layout thereof and method of manufacturing same

Multiplier-accumulator processing pipelines and processing component, and methods of operating same

Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA

Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA

Modular field programmable gate array, and method of configuring and operating same

Mac processing pipeline having conversion circuitry, and methods of operating same

Multiplier-accumulator processing pipelines and processing component, and methods of operating same

Multiplier-accumulator processing pipelines and processing component, and methods of operating same

MAC processing pipelines, circuitry to control and configure same, and methods of operating same

Multiplier-accumulator circuitry having processing pipelines and methods of operating same

MAC processing pipelines, circuitry to control and configure same, and methods of operating same

Test circuitry and techniques for logic tiles of FPGA

Multiplier-accumulator circuitry having processing pipelines and methods of operating same

Test circuitry and techniques for logic tiles of FPGA

Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA

Clock distribution and generation architecture for logic tiles of an integrated circuit and method of operating same

MAC processing pipeline using filter weights having enhanced dynamic range, and methods of operating same

ANALOG DEVICES INC

MAC processing pipelines, circuitry to configure same, and methods of operating same

Coarse floating point accumulator circuit, and MAC processing pipelines including same

MAC processing pipeline having activation circuitry, and methods of operating same

Multiplier-accumulator circuitry, and processing pipeline including same

Modular field programmable gate array, and method of configuring and operating the same

Configurable MAC pipelines for finite-impulse-response filtering, and methods of operating same

INTEL CORP

Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliability

Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints

Apparatus and method for redundant software thread computation

WANG CHENG C

Inflatable pool

Inflatable article with edge concealing means

Portable multi-function apparatus

FLEX LOGIX TECHNOLOGIES INC

Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof