Modular field programmable gate array, and method of configuring and operating the same

Abstract

An integrated circuit comprising an FPGA including programmable/configurable logic circuitry having a periphery, wherein resources (e.g., memory (e.g., high-speed local RAM), one or more busses, and/or circuitry external to the FPGA (e.g., a processor, a controller and/or system/external memory), is/are disposed outside the periphery of the programmable/configurable logic circuitry which includes a plurality of logic tiles, wherein at least one logic tile is located completely within the interior of the periphery and wherein each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery, and the first portion of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide communication between the resources and the logic tiles.

What is claimed is: 
     
       1. An integrated circuit comprising:
 a bus; 
 a processor, wherein the processor is connected to the bus; and 
 programmable/configurable logic circuitry having a periphery, wherein the processor is disposed outside the periphery of the programmable/configurable logic circuitry, the programmable/configurable logic circuitry includes:
 a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein at least one logic tile of the plurality of logic tiles is located completely within the interior of the periphery of the programmable/configurable logic circuitry and wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery of the programmable/configurable logic circuitry, and 
 the first portion of the plurality of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide data communication between the processor and the plurality of logic tiles; and 
 
 
 wherein the bus is routed between each of the plurality of rows of logic tiles of the plurality of logic tiles. 
 
     
     
       2. The integrated circuit of  claim 1  wherein:
 the bus is a multi-drop bus wherein the processor is configurable to provide direct communication to each logic tile of the plurality of logic tiles. 
 
     
     
       3. The integrated circuit of  claim 1  wherein:
 the bus is a point-to-point bus wherein the processor is configurable to provide direct communication to each logic tile of the plurality of logic tiles. 
 
     
     
       4. The integrated circuit of  claim 1  wherein:
 the bus is routed between each of the plurality of columns of logic tiles of the plurality of logic tiles. 
 
     
     
       5. The integrated circuit of  claim 1  wherein:
 the processor is programmable to transmit re-configuration data to each logic tile of the plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to provide a modular computing array architecture. 
 
     
     
       6. An integrated circuit comprising:
 a multi-drop bus; 
 a processor, wherein the processor is connected to the multi-drop bus; and 
 programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein the logic tiles form a periphery of the programmable/configurable logic circuitry, wherein the processor is disposed outside the periphery of the programmable/configurable logic circuitry, and wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile, wherein:
 a first portion of the plurality of I/Os of the plurality of logic tiles are located on a perimeter of the logic tiles that is located interior to the periphery of the programmable/configurable logic circuitry, and 
 a second portion of the I/Os of a subset of the plurality of logic tiles are located on a perimeter of the logic tiles that is located on the periphery of the programmable/configurable logic circuitry; and 
 
 
 wherein the multi-drop bus is:
 routed between each of the plurality of rows or each of the plurality of columns of logic tiles of the plurality of logic tiles, and 
 directly connected to a plurality of the first portion of I/Os of each logic tile of the plurality of logic tiles to provide data communication between the processor and the plurality of logic tiles. 
 
 
     
     
       7. The integrated circuit of  claim 6  wherein:
 the processor is configurable to programmable to transmit re-configuration data to each logic tile of the plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to provide a modular computing array architecture. 
 
     
     
       8. The integrated circuit of  claim 6  wherein:
 the second portion of the I/Os of a subset of the plurality of logic tiles are configurable to provide direct communication to circuitry external to the programmable/configurable logic circuitry. 
 
     
     
       9. The integrated circuit of  claim 6  further including:
 a plurality of block random access memories, wherein each logic tile of the plurality of logic tiles is directly connected to and associated with a unique block random access memory. 
 
     
     
       10. The integrated circuit of  claim 9  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein:
 the memory bus is configurable to provide direct communication with each block random access memory during operation of the programmable/configurable logic circuitry. 
 
 
     
     
       11. The integrated circuit of  claim 10  wherein:
 each block random access memory of the plurality of block random access memories includes dual-port memory for direct access from the memory bus and by circuitry of the associated logic tile. 
 
     
     
       12. The integrated circuit of  claim 6  further including:
 a plurality of block random access memories, wherein each block random access memory is adjacent and directly connected to a logic tile of the plurality of logic tiles. 
 
     
     
       13. The integrated circuit of  claim 12  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein:
 the memory bus is capable of communicating with each block random access memory during operation of the programmable/configurable logic circuitry. 
 
 
     
     
       14. The integrated circuit of  claim 12  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein the memory bus is a point-to-point bus. 
 
     
     
       15. An integrated circuit comprising:
 a bus; 
 a processor, wherein the processor is connected to the bus; and 
 programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein the logic tiles form a periphery of the programmable/configurable logic circuitry, wherein the processor is disposed outside the periphery of the programmable/configurable logic circuitry, wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile, wherein a first portion of the plurality of I/Os of the plurality of the logic tiles are located on a perimeter of the logic tiles that is located interior to the periphery of the programmable/configurable logic circuitry wherein a plurality of the first portion of I/Os directly connect to the bus to provide data communication to/from the processor, and 
 
 wherein the bus is:
 connected to a plurality of block random access memories, wherein each block random access memory is directly connected to and associated with a logic tile of the plurality of logic tiles, and 
 routed between (i) a plurality of rows of logic tiles of the plurality of logic tiles or (ii) a plurality of columns of logic tiles of the plurality of logic tiles. 
 
 
     
     
       16. The integrated circuit of  claim 15  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein the memory bus is capable of communicating with each block random access memory during operation of the programmable/configurable logic circuitry. 
 
     
     
       17. The integrated circuit of  claim 15  wherein:
 the processor is programmable to transmit re-configuration data to each logic tile of the first plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to provide a modular computing array architecture. 
 
     
     
       18. The integrated circuit of  claim 15  wherein:
 the bus is a multi-drop bus wherein the processor is configurable to provide direct communication to at least a subset of the plurality of logic tiles. 
 
     
     
       19. The integrated circuit of  claim 15  wherein:
 the bus is a point-to-point bus wherein the processor is configurable to provide direct communication to at least a subset of the plurality of logic tiles. 
 
     
     
       20. An integrated circuit comprising:
 a bus; 
 a processor, wherein the processor is connected to the bus; 
 programmable/configurable logic circuitry having a periphery, wherein the processor is disposed outside the periphery of the programmable/configurable logic circuitry, the programmable/configurable logic circuitry includes:
 a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein at least one logic tile of the plurality of logic tiles is located completely within the interior of the periphery of the programmable/configurable logic circuitry and wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery of the programmable/configurable logic circuitry, and 
 the first portion of the plurality of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide data communication between the processor and the plurality of logic tiles; and 
 
 
 wherein the bus is routed between each of the plurality of columns of logic tiles of the plurality of logic tiles. 
 
     
     
       21. The integrated circuit of  claim 20  wherein:
 the bus is a multi-drop bus wherein the processor is configurable to provide direct communication to each logic tile of the plurality of logic tiles. 
 
     
     
       22. The integrated circuit of  claim 20  wherein:
 the bus is a point-to-point bus wherein the processor is configurable to provide direct communication to each logic tile of the plurality of logic tiles. 
 
     
     
       23. The integrated circuit of  claim 20  wherein:
 the processor is programmable to transmit re-configuration data to each logic tile of the plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to provide a modular computing array architecture. 
 
     
     
       24. An integrated circuit comprising:
 a bus;   a controller, wherein the controller is connected to the bus; and   programmable/configurable logic circuitry having a periphery, wherein the controller is disposed outside the periphery of the programmable/configurable logic circuitry, the programmable/configurable logic circuitry includes:
 a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein at least one logic tile of the plurality of logic tiles is located completely within the interior of the periphery of the programmable/configurable logic circuitry and wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os, and 
 a first portion of the plurality of I/Os of each logic tile of the plurality of the logic tiles is configurable to directly connect to the bus to provide direct communication to or from the controller; and 
 
   wherein the bus is routed between each of the plurality of rows of logic tiles of the plurality of logic tiles.   
     
     
       25. The integrated circuit of  claim 24  wherein:
 the bus is a multi-drop bus or a point-to-point bus wherein the controller is configurable to directly connect to each logic tile of the plurality of logic tiles. 
 
     
     
       26. The integrated circuit of  claim 24  wherein:
 the controller is configurable to directly connect to each logic tile of the plurality of logic tiles. 
 
     
     
       27. The integrated circuit of  claim 24  wherein:
 the bus is further routed between each of the plurality of columns of logic tiles of the plurality of logic tiles. 
 
     
     
       28. The integrated circuit of  claim 24  wherein;
 wherein a first portion of the plurality of I/Os is located on a perimeter of the logic tile that is interior to the periphery of the programmable/configurable logic circuitry. 
 
     
     
       29. An integrated circuit comprising:
 a bus;   a controller, wherein the controller is connected to the bus; and   programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein the logic tiles form a periphery of the programmable/configurable logic circuitry, wherein the controller is disposed outside the periphery of the programmable/configurable logic circuitry, and wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile, wherein:
 a first portion of the plurality of I/Os of each logic tile of the plurality of logic tiles is located on a perimeter of the logic tile that is located interior to the periphery of the programmable/configurable logic circuitry; and 
 
   wherein the bus is:
 routed between each of the plurality of rows and each of the plurality of columns of logic tiles of the plurality of logic tiles, and 
 directly connected to a plurality of I/Os of the first portion of I/Os of each logic tile of the plurality of logic tiles to provide data communication to the controller. 
   
     
     
       30. The integrated circuit of  claim 29  wherein:
 the bus is a multi-drop or a point-to-point bus. 
 
     
     
       31. The integrated circuit of  claim 29  wherein:
 a second portion of the I/Os of each logic tile of a subset of the plurality of logic tiles is located on a perimeter of the logic tiles that is located on the periphery of the programmable/configurable logic circuitry: 
 the second portion of the I/Os of each logic tile of the subset of the plurality of logic tiles is configurable to provide direct communication to circuitry external to the programmable/configurable logic circuitry. 
 
     
     
       32. The integrated circuit of  claim 29  further including:
 a plurality of block random access memories, wherein each logic tile of the plurality of logic tiles is directly connected to and associated with a unique block random access memory. 
 
     
     
       33. The integrated circuit of  claim 32  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein:
 the memory bus is configurable to provide direct communication with each block random access memory during operation of the programmable/configurable logic circuitry. 
 
 
     
     
       34. The integrated circuit of  claim 33  wherein:
 each block random access memory of the plurality of block random access memories includes dual-port memory for direct access from the memory bus and by circuitry of the associated logic tile. 
 
     
     
       35. The integrated circuit of  claim 29  further including:
 a plurality of block random access memories, wherein each block random access memory is adjacent and directly connected to a logic tile of the plurality of logic tiles. 
 
     
     
       36. The integrated circuit of  claim 35  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein:
 the memory bus is capable of communicating with each block random access memory during operation of the programmable/configurable logic circuitry. 
 
 
     
     
       37. The integrated circuit of  claim 35  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein the memory bus is a point-to-point bus. 
 
     
     
       38. An integrated circuit comprising:
 a bus;   a controller, wherein the controller is connected to the bus; and   programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein the logic tiles form a periphery of the programmable/configurable logic circuitry, wherein the controller is disposed outside the periphery of the programmable/configurable logic circuitry, wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile, wherein a first portion of the plurality of I/Os of the plurality of the logic tiles is located on a perimeter of the logic tiles that is located interior to the periphery of the programmable/configurable logic circuitry wherein a plurality of the first portion of I/Os directly connect to the bus to provide data communication to/from the controller, and 
   wherein the bus is:
 connected to a plurality of block random access memories, wherein each block random access memory is directly connected to and associated with a logic tile of the plurality of logic tiles, and 
 routed between (i) a plurality of rows of logic tiles of the plurality of logic tiles or (ii) a plurality of columns of logic tiles of the plurality of logic tiles. 
   
     
     
       39. The integrated circuit of  claim 38  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein the memory bus is capable of communicating with each block random access memory during operation of the programmable/configurable logic circuitry. 
 
     
     
       40. The integrated circuit of  claim 38  wherein:
 the controller is programmable to transmit re-configuration data to each logic tile of a first plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to configure the first plurality of logic tiles into a first modular computing array. 
 
     
     
       41. The integrated circuit of  claim 38  wherein:
 the bus is a multi-drop bus, and wherein the controller is configurable to directly connect to at least a subset of the plurality of logic tiles. 
 
     
     
       42. The integrated circuit of  claim 38  wherein:
 the bus is a point-to-point bus, and wherein the controller is configurable to directly connect to at least a subset of the plurality of logic tiles. 
 
     
     
       43. An integrated circuit comprising:
 a bus;   a controller, wherein the controller is connected to the bus; and   programmable/configurable logic circuitry having a periphery, wherein the controller is disposed outside the periphery of the programmable/configurable logic circuitry, the programmable/configurable logic circuitry includes:
 a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein at least one logic tile of the plurality of logic tiles is located completely within the interior of the periphery of the programmable/configurable logic circuitry and wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os, and 
 a first portion of the plurality of I/Os of each logic tile of the plurality of the logic tiles is configurable to directly connect to the bus to provide direct communication to or from the controller; and 
 
   wherein the bus is routed between each of the plurality of columns of logic tiles of the plurality of logic tiles.   
     
     
       44. The integrated circuit of  claim 43  wherein: the bus is a multi-drop bus or a point-to-point bus. 
     
     
       45. The integrated circuit of  claim 43  wherein:
 a first portion of the plurality of I/Os is located on a perimeter of the logic tile that is interior to the periphery of the programmable/configurable logic circuitry. 
 
     
     
       46. The integrated circuit of  claim 43  wherein:
 the controller is programmable to transmit re-configuration data to each logic tile of the plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to configure one or more logic tiles into a first modular computing array. 
 
     
     
       47. An integrated circuit comprising:
 a bus; and   programmable/configurable logic circuitry having a periphery, configurable to directly connect to a controller which is disposed outside the periphery of the programmable/configurable logic circuitry, the programmable/configurable logic circuitry includes:
 a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein at least one logic tile of the plurality of logic tiles is located completely within the interior of the periphery of the programmable/configurable logic circuitry and wherein: 
 each logic tile of the array of logic tiles includes a plurality of I/Os, and 
 a first portion of the plurality of I/Os of each logic tile of the plurality of the logic tiles is configurable to directly connect to the bus to provide direct communication to or from the controller; and 
   wherein the bus is routed between (i) each of the plurality of rows of logic tiles of the plurality of logic tiles or (ii) each of the plurality of columns of logic tiles of the plurality of logic tiles.   
     
     
       48. The integrated circuit of  claim 47  wherein:
 the bus is a multi-drop bus or a point-to-point bus wherein the controller is configurable to directly connect to each logic tile of the plurality of logic tiles. 
 
     
     
       49. The integrated circuit of  claim 47  wherein:
 the controller is configurable to directly connect to each logic tile of the plurality of logic tiles. 
 
     
     
       50. The integrated circuit of  claim 47  wherein:
 the bus is further routed between each of the plurality of columns of logic tiles of the plurality of logic tiles. 
 
     
     
       51. The integrated circuit of  claim 47  wherein:
 wherein a first portion of the plurality of I/Os is located on a perimeter of the logic tile that is interior to the periphery of the programmable/configurable logic circuitry. 
 
     
     
       52. An integrated circuit comprising:
 a bus; and   programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein the logic tiles form a periphery of the programmable/configurable logic circuitry and the programmable/configurable logic circuitry is configurable to directly connect to a controller which is disposed outside the periphery of the programmable/configurable logic circuitry, and wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile, wherein:
 a first portion of the plurality of I/Os of each logic tile of the plurality of logic tiles is located on a perimeter of the logic tile that is located interior to the periphery of the programmable/configurable logic circuitry; and 
 
   wherein the bus is:
 routed between each of the plurality of rows and each of the plurality of columns of logic tiles of the plurality of logic tiles, and 
 directly connected to a plurality of I/Os of the first portion of I/Os of each logic tile of the plurality of logic tiles to provide data communication to the controller. 
   
     
     
       53. The integrated circuit of  claim 52  wherein:
 the bus is a multi-drop or a point-to-point bus. 
 
     
     
       54. The integrated circuit of  claim 52  wherein:
 a second portion of the I/Os of each logic tile of a subset of the plurality of logic tiles is located on a perimeter of the logic tiles that is located on the periphery of the programmable/configurable logic circuitry: 
 the second portion of the I/Os of each logic tile of the subset of the plurality of logic tiles is configurable to provide direct communication to circuitry external to the programmable/configurable logic circuitry. 
 
     
     
       55. The integrated circuit of  claim 52  further including:
 a plurality of block random access memories, wherein each logic tile of the plurality of logic tiles is directly connected to and associated with a unique block random access memory. 
 
     
     
       56. The integrated circuit of  claim 55  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein:
 the memory bus is configurable to provide direct communication with each block random access memory during operation of the programmable/configurable logic circuitry. 
 
 
     
     
       57. The integrated circuit of  claim 56  wherein:
 each block random access memory of the plurality of block random access memories includes dual-port memory for direct access from the memory bus and by circuitry of the associated logic tile. 
 
     
     
       58. The integrated circuit of  claim 52  further including:
 a plurality of block random access memories, wherein each block random access memory is adjacent and directly connected to a logic tile of the plurality of logic tiles. 
 
     
     
       59. The integrated circuit of  claim 58  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein:
 the memory bus is capable of communicating with each block random access memory during operation of the programmable/configurable logic circuitry. 
 
 
     
     
       60. The integrated circuit of  claim 58  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein the memory bus is a point-to-point bus. 
 
     
     
       61. An integrated circuit comprising:
 a bus; and   programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein the logic tiles form a periphery of the programmable/configurable logic circuitry and the programmable/configurable logic circuitry is configurable to directly connect to a controller which is disposed outside the periphery of the programmable/configurable logic circuitry, wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile, wherein a first portion of the plurality of I/Os of the plurality of the logic tiles is located on a perimeter of the logic tiles that is located interior to the periphery of the programmable/configurable logic circuitry wherein a plurality of the first portion of I/Os directly connect to the bus to provide data communication to/from the controller, and 
   wherein the bus is:
 connected to a plurality of block random access memories, wherein each block random access memory is directly connected to and associated with a logic tile of the plurality of logic tiles, and 
 routed between (i) a plurality of rows of logic tiles of the plurality of logic tiles or (ii) a plurality of columns of logic tiles of the plurality of logic tiles. 
   
     
     
       62. The integrated circuit of  claim 61  further including:
 a memory bus, located adjacent to each block random access memory of the plurality of block random access memories to directly connect to the block random access memory wherein the memory bus is capable of communicating with each block random access memory during operation of the programmable/configurable logic circuitry. 
 
     
     
       63. The integrated circuit of  claim 61  wherein:
 the controller is programmable to transmit re-configuration data to each logic tile of a first plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to configure the first plurality of logic tiles into a first modular computing array. 
 
     
     
       64. The integrated circuit of  claim 61  wherein:
 the bus is a multi-drop bus, and wherein the controller is configurable to directly connect to at least a subset of the plurality of logic tiles. 
 
     
     
       65. The integrated circuit of  claim 61  wherein:
 the bus is a point-to-point bus, and wherein the controller is configurable to directly connect to at least a subset of the plurality of logic tiles. 
 
     
     
       66. An integrated circuit comprising:
 a bus; and   programmable/configurable logic circuitry having a periphery and configurable to directly connect to a controller which is disposed outside a periphery of the programmable/configurable logic circuitry, wherein the programmable/configurable logic circuitry includes:   a plurality of logic tiles, arranged in an array having a plurality of rows and columns. wherein at least one logic tile of the plurality of logic tiles is located completely within the interior of the periphery of the programmable/configurable logic circuitry and wherein:
 each logic tile of the array of logic tiles includes a plurality of I/Os, and 
 a first portion of the plurality of I/Os of each logic tile of the plurality of the logic tiles is configurable to directly connect to the bus to provide direct communication to or from the controller; and 
   wherein the bus is routed between each of the plurality of columns of logic tiles of the plurality of logic tiles.   
     
     
       67. The integrated circuit of  claim 66  wherein:
 the bus is a multi-drop bus or a point-to-point bus. 
 
     
     
       68. The integrated circuit of  claim 66  wherein:
 a first portion of the plurality of I/Os is located on a perimeter of the logic tile that is interior to the periphery of the programmable/configurable logic circuitry. 
 
     
     
       69. The integrated circuit of  claim 66  wherein:
 the controller is programmable to transmit re-configuration data to each logic tile of the plurality of logic tiles, after initialization of the programmable/configurable logic circuitry, to configure one or more logic tiles into a first modular computing array. 
 
     
     
       70. A system comprising:
 a bus;   a controller, disposed on a first die, wherein the controller is connected to the bus; and   a programmable/configurable logic circuitry, disposed on a second die, the programmable/configurable logic circuitry having a periphery, wherein the controller is disposed outside the periphery of the programmable/configurable logic circuitry, the programmable/configurable logic circuitry includes:
 a plurality of logic tiles, arranged in an array having a plurality of rows and columns, wherein at least one logic tile of the plurality of logic tiles is located completely within the interior of the periphery of the programmable/configurable logic circuitry and wherein: 
 each logic tile of the array of logic tiles includes a plurality of I/Os, and 
 a first portion of the plurality of I/Os of each logic tile of the plurality of the logic tiles is configurable to directly connect to the bus to provide direct communication to or from the controller; and 
   wherein the bus is routed between (i) each of the plurality of rows of logic tiles of the plurality of logic tiles or (ii) each of the plurality of columns of logic tiles of the plurality of logic tiles.   
     
     
       71. The integrated circuit of  claim 70  wherein:
 the controller and the programmable/configurable logic circuitry are attached in a stacked die configuration. 
 
     
     
       72. The integrated circuit of  claim 71  wherein:
 the controller and the programmable/configurable logic circuitry are configured co-planar.