Inventor · disambiguated record
Mary E. Weybright
Also filed as: WEYBRIGHT MARY · WEYBRIGHT MARY E · WEYBRIGHT MARY ELIZABETH
21 granted patents·1 pending application·618 citations·filing 1998–2020
96Inventor score
Top patents by PatentIndex Score
22 records- 0198US9564446B1SRAM design to facilitate single fin cut in double sidewall image transfer processIBM·Filed 2015·Granted Feb 7, 2017·34 cites·14 claims
- 0295US6190979B1Method for fabricating dual workfunction devices on a semiconductor substrate using counter-doping and gapfillIBM·Filed 1999·Granted Feb 20, 2001·186 cites·22 claims
- 0393US6388294B1Integrated circuit using damascene gate structureIBM·Filed 2000·Granted May 14, 2002·69 cites·10 claims
- 0488US6504210B1Fully encapsulated damascene gates for Gigabit DRAMsIBM·Filed 2000·Granted Jan 7, 2003·48 cites·8 claims
- 0586US6403423B1Modified gate processing for optimized definition of array and logic devices on same chipIBM·Filed 2000·Granted Jun 11, 2002·38 cites·30 claims
- 0683US6458646B1Asymmetric gates for high density DRAMIBM·Filed 2000·Granted Oct 1, 2002·30 cites·15 claims
- 0781US6548357B2Modified gate processing for optimized definition of array and logic devices on same chipIBM·Filed 2002·Granted Apr 15, 2003·28 cites·18 claims
- 0879US6261972B1Dual gate oxide process for uniform oxide thicknessINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jul 17, 2001·27 cites·12 claims
- 0979US6194301B1Method of fabricating an integrated circuit of logic and memory using damascene gate structureIBM·Filed 1999·Granted Feb 27, 2001·49 cites·16 claims
- 1074US10096521B2SRAM design to facilitate single fin cut in double sidewall image transfer processIBM·Filed 2017·Granted Oct 9, 2018·1 cites·6 claims
- 1174US6930004B2Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scalingIBM·Filed 2003·Granted Aug 16, 2005·16 cites·20 claims
- 1272US6326260B1Gate prespacers for high density, high performance DRAMsIBM·Filed 2000·Granted Dec 4, 2001·16 cites·14 claims
- 1371USRE49794ESRAM design to facilitate single fin cut in double sidewall image transfer processADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2020·Granted Jan 9, 2024·0 cites·36 claims
- 1468US6724053B1PMOSFET device with localized nitrogen sidewall implantationIBM·Filed 2000·Granted Apr 20, 2004·12 cites·9 claims
- 1564US6180975B1Depletion strap semiconductor memory deviceIBM·Filed 1998·Granted Jan 30, 2001·20 cites·16 claims
- 1655US6197632B1Method for dual sidewall oxidation in high density, high performance DRAMSIBM·Filed 1999·Granted Mar 6, 2001·14 cites·12 claims
- 1752US6346734B2Modified gate conductor processing for poly length control in high density DRAMSIBM·Filed 1999·Granted Feb 12, 2002·13 cites·16 claims
- 1850US6380027B2Dual tox trench dram structures and process using V-grooveIBM·Filed 1999·Granted Apr 30, 2002·10 cites·25 claims
- 1946US6670667B2Asymmetric gates for high density DRAMIBM·Filed 2002·Granted Dec 30, 2003·2 cites·13 claims
- 2043US6656798B2Gate processing method with reduced gate oxide corner and edge thinningINFINEON TECHNOLOGIES AG·Filed 2001·Granted Dec 2, 2003·1 cites·8 claims
- 2136US2001054729A1Gate prespacers for high density, high performance dramsIBM·Filed 2001·Application pending·0 cites
- 2234US6096664AMethod of manufacturing semiconductor structures including a pair of MOSFETsSIEMENS AG·Filed 1998·Granted Aug 1, 2000·4 cites·26 claims
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