Gate prespacers for high density, high performance drams

Abstract

A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.

Having thus described our invention in detail, what we claim as new and desire to secure by the Letters Patent is:  
     
         1 . A method of forming a gate conductor useful in a semiconductor memory device comprising the steps of: 
 (a) providing a semiconductor structure including at least a gate oxide layer formed on a surface of a semiconductor substrate, said structure being divided into array regions and support regions which may have different oxide thicknesses;    (b) forming a gate stack on said structure, said gate stack including a layer of polysilicon formed on the gate oxide layer, a conductor material layer formed on said layer of polysilicon, and a nitride cap layer formed on said conductor material layer;    (c) partially mask open etching the gate stack by patterning the nitride cap layer and etching through the gate stack stopping on said layer of polysilicon;    (d) forming spacers on exposed sidewalls of said partially etched gate stack;    (e) completing said mask open etching in said array regions by removing any exposed polysilicon, while not etching said layer of polysilicon in the support regions;    (f) performing a first oxidation step on the structure so as to form an oxide layer on exposed polysilicon sidewalls in said array regions while simultaneously forming a sacrificial oxide layer on said layer of polysilicon in said support regions;    (g) selectively removing said spacers in said support regions of said structure;    (h) selectively removing said sacrificial oxide layer and said layer of polysilicon in said support regions; and    (i) performing a second oxidization step on said structure so as to form an array oxide layer and a support oxide layer, said array oxide layer having a thickness that is greater than the support oxide layer, said array oxide layer comprising oxide layers from said first and second oxidation steps.    
     
     
         2 . The method of    claim 1    wherein said gate oxide layer is formed by a thermal growing process or a deposition process selected from the group consisting of CVD, plasma-assisted CVD, sputtering and evaporation.  
     
     
         3 . The method of    claim 1    wherein said gate stack is formed by the same or different deposition process selected from the group consisting of CVD, plasma-assisted CVD, plating, sputtering and evaporation.  
     
     
         4 . The method of    claim 1    wherein an optional barrier layer is formed on said layer of polysilicon prior to forming said conductor material layer.  
     
     
         5 . The method of    claim 1    wherein said layer of polysilicon is doped by an in-situ deposition doping process or deposition followed by implantation.  
     
     
         6 . The method of    claim 1    wherein step (c) includes lithography and etching.  
     
     
         7 . The method of    claim 1    wherein said spacers are formed by deposition and etching.  
     
     
         8 . The method of    claim 7    wherein said etching occurs during step (e).  
     
     
         9 . The method of    claim 1    wherein step (e) includes an anisotropic etching process.  
     
     
         10 . The method of    claim 1    wherein said first oxidation step is carried out at a temperature of greater than 850° C. in an oxidizing ambient.  
     
     
         11 . The method of    claim 10    wherein said first oxidation step is carried out at a temperature of greater than 900° C.  
     
     
         12 . The method of    claim 1    wherein step (g) includes the use of an isotropic etch process.  
     
     
         13 . The method of    claim 1    wherein said second oxidation step is carried out at a temperature of greater than 850° C. in an oxidizing ambient.  
     
     
         14 . The method of    claim 13    wherein said second oxidation step is carried out at a temperature of greater than 900° C.  
     
     
         15 . A gate conductor structure comprising: 
 a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions,    said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer on said gate oxide layer, a conductor material layer on said polysilicon layer, and a nitride cap layer on said conductor material layer, said nitride cap layer and said conductor material layer having spacers on sidewalls thereof and said polysilicon layer having an array oxide layer on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, and    said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.    
     
     
         16 . The gate conductor structure of    claim 15    wherein said substrate is composed of a semiconductor material selected from the group consisting of Si, Ge, SiGe, GaAs, InAs and layered substrates.  
     
     
         17 . The gate conductor structure of    claim 15    wherein said conductor material layer is composed of an elemental metal, a metal silicide, a metal nitride, or combinations thereof.  
     
     
         18 . The gate conductor structure of    claim 17    wherein said conductor material layer is composed of tungsten silicide.  
     
     
         19 . The gate conductor structure of    claim 15    wherein said array oxide layer has a thickness of from about 5 to about 25 nm and said support oxide layer has a thickness of from about 3 to about 10 nm.  
     
     
         20 . The gate conductor structure of    claim 15    wherein said spacers are composed of a nitride-containing material.  
     
     
         21 . The gate conductor structure of    claim 20    wherein said spacers are composed of SiN.  
     
     
         22 . The gate conductor structure of    claim 15    wherein said cap nitride layer is composed of SiN.