Inventor

TIGELAAR HOWARD L

US53 patents

⚠️ This page may combine multiple inventors who share the name “TIGELAAR HOWARD L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TIGELAAR HOWARD L

TEXAS INSTRUMENTS INC

Four memory state EEPROM

EPROM with increased floating gate/control gate coupling

Process for thickening selective gate oxide regions

Method of making contract-free floating-gate memory array with silicided buried bitlines and with single-step defined floating gates

Method of making metal-to-polysilicon capacitor

Non-volatile memory with improved coupling between gates

Floating gate memory cell and device

Method of making a pleated floating gate trench EPROM

High speed EPROM with reverse polarity voltages applied to source and drain regions during reading and writing

Method of making planarized EPROM array

Floating gate memory cell and device

Integrated circuit process with TiN-gate transistor

X-cell EEPROM array

Stacked capacitor

Integrated circuit device and process with tin capacitors

Fabricating a stacked capacitor

Metal-to-metal antifuse structure

Apparatus for and method of rapid testing of semiconductor components at elevated temperature

Floating-gate memory array with silicided buried bitlines

Split metal plate capacitor and method for making the same

Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates

Metal plate capacitor and method for making the same

Metal-to-polysilicon capacitor and method for making the same

Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates

Metal plate capacitor and method for making the same

Programmable gate array and methods for its fabrication

EPROM with increased floating gate/control gate coupling

Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment

Integrated circuit device and process with tin-gate transistor

Device and process with doubled capacitors

Metal-to-metal antifuse structure

Electrically erasable programmable read only memory cell including trench capacitor

Method for improving wafer sleuth capability by adding wafer rotation tracking

Sidewall oxide to reduce filaments

Method of making high speed EPROM containing graded source/drain profile

Method of making flash EEPROM or merged FAMOS cell without alignment sensitivity

Contact-free floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates

Method of making an array device with buried interconnects

Method of fabricating microelectronic device incorporating capacitor having lowered topographical profile

Use of sidewall oxide to reduce filaments

Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices

Non-volatile memory cell with tunnel window structure and method

Optimized metal fuse process

Feedback structure for an SRAM cell

Method for patterning dense and isolated features on semiconductor devices

Floating-gate memory array with silicided buried bitlines

Dummy active area implementation

Method for reduction of filaments between electrodes

ROHM & HAAS

Process for preparing highly filled acrylic articles

TIGELAAR HOWARD L

Single-polysilicon dram device and process