Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices

Abstract

A method ( 100 ) of forming fully-depleted ( 90 ) and partially-depleted ( 92 ) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device ( 2 ) is disclosed using SOI starting material ( 4, 6, 8 ) and a selective epitaxial growth process ( 110 ).

1. A method of forming fully-depleted and partially-depleted silicon-on-insulator (SOI) devices in an integrated circuit device, comprising:
 providing a first silicon layer over a buried oxide layer, wherein the silicon layer comprises a first thickness associated with a fully-depleted SOI device, the first silicon layer having a fully-depleted region and a partially-depleted region associated therewith; 
 forming a dielectric portion over the first silicon layer in the fully-depleted region; 
 forming a second silicon layer over the first silicon layer, thereby surrounding the dielectric portion in the fully-depleted region and forming a composite silicon layer comprising the first and second silicon layers in the partially-depleted region, wherein the composite silicon layer has a second thickness associated with a partially-depleted SOI device; 
 forming a dielectric layer over the second silicon layer, thereby covering the composite silicon layer in the partially-depleted region and surrounding the dielectric portion in the fully-depleted region; 
 removing the dielectric portion in the fully-depleted region and a portion of the dielectric layer in the partially-depleted region, thereby forming a fully-depleted gate opening and exposing a portion of the first silicon layer in the fully-depleted region and forming a partially-depleted gate opening and exposing a portion of the second silicon layer in the partially-depleted region; 
 providing insulating material on sidewalls of the gate openings; and 
 forming conductive material in the gate openings, thereby forming fully-depleted and partially-depleted gate electrodes therein, respectively, wherein a distance between a bottom of the fully-depleted gate electrode and the buried oxide layer is less than a distance between a bottom of the partially-depleted gate electrode and the buried oxide layer. 
 
   
   
     2. The method of  claim 1 , wherein the dielectric portion comprises a nitride material and the dielectric layer comprises an oxide material. 
   
   
     3. The method of  claim 1 , wherein forming the second silicon layer comprises performing a selective epitaxial deposition, wherein silicon grows on surfaces containing silicon and does not grow substantially on surfaces that do not contain silicon, whereby the second silicon layer does not grow on a top part of the dielectric portion. 
   
   
     4. The method of  claim 1 , wherein forming the dielectric layer comprises:
 depositing a dielectric material over the device; and 
 planarizing the dielectric material until a top portion of the dielectric portion is exposed. 
 
   
   
     5. The method of  claim 1 , wherein removing the portion of the dielectric layer in the partially-depleted region comprises:
 forming a patterned photoresist or hardmask layer over the dielectric layer; and 
 etching the dielectric layer using the patterned photoresist or hardmask layer as an etch mask down to the second silicon layer to form the partially-depleted gate opening. 
 
   
   
     6. The method of  claim 5 , wherein the dielectric layer comprises an oxide material and the dielectric portion comprises a nitride material, wherein removing the dielectric portion comprises etching the nitride material dielectric portion with an etchant that is substantially selective with respect to the oxide material. 
   
   
     7. The method of  claim 1 , further comprising:
 forming a sacrificial oxide layer in the fully-depleted gate opening, wherein the sacrificial oxide consumes a portion of the first silicon layer at the bottom of the fully-depleted gate opening; and 
 removing the sacrificial oxide, thereby again exposing the first silicon layer at the bottom of the fully-depleted gate opening, wherein a remaining thickness of the first silicon layer below the fully-depleted gate opening is small enough to ensure fully depletion thereat during device operation. 
 
   
   
     8. The method of  claim 1 , further comprising forming a gate oxide at a bottom of the gate openings. 
   
   
     9. The method of  claim 1 , wherein providing insulating material on sidewalls of the gate openings comprises:
 depositing a nitride layer in a generally conformal manner over a remaining top portion of the dielectric layer and in the gate openings; and 
 performing a substantially anisotropic etch of the nitride layer, thereby removing portions of the nitride layer on the top of the dielectric layer and at the bottom of the gate openings and leaving nitride material on the sidewalls of the gate openings. 
 
   
   
     10. The method of  claim 1 , wherein forming conductive material in the gate openings comprises:
 depositing a polysilicon layer over the dielectric layer and in the gate openings; and 
 planarizing the polysilicon layer down to the top of the dielectric layer, thereby isolating the polysilicon in the gate openings. 
 
   
   
     11. The method of  claim 1 , further comprising:
 forming a pad oxide layer over the first silicon layer prior to forming the dielectric portion in the fully-depleted region; and 
 performing a pad oxide etch after forming the dielectric portion thereover, wherein a remaining portion of the pad oxide is recessed under the dielectric portion. 
 
   
   
     12. The method of  claim 11 , wherein upon removing the dielectric portion in the fully-depleted region, the recessed pad oxide remains at the bottom of the fully-depleted gate opening, and further comprising performing an extension region implant into the fully-depleted gate opening, thereby forming extension regions in the first silicon layer below the fully-depleted gate opening having a spacing therebetween corresponding to a width of the recessed pad oxide. 
   
   
     13. The method of  claim 12 , further comprising:
 removing the recessed pad oxide after the extension region implant; and 
 performing a threshold voltage adjust implant into the first silicon layer at the bottom of the fully-depleted gate opening and into the second silicon layer at the bottom of the partially-depleted gate opening. 
 
   
   
     14. The method of  claim 1 , further comprising:
 removing a portion of the dielectric layer to a level to expose the underlying second silicon layer, thereby exposing the gate electrodes vertically extending therefrom; 
 performing an extension region implant into the second silicon material to form extension regions for the fully-depleted and partially-depleted devices; 
 forming sidewall spacers along sidewalls of the gate electrodes; and 
 performing a source/drain implant into the second silicon material to form source/drain regions for the fully-depleted and partially-depleted devices spaced apart from the gate electrodes a distance corresponding to a width of the sidewall spacers.