Inventor

WRISTERS DERICK J

US138 patents

⚠️ This page may combine multiple inventors who share the name “WRISTERS DERICK J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WRISTERS DERICK J

ADVANCED MICRO DEVICES INC

Method and apparatus for in situ anneal during ion implant

Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer

Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate

Method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements

Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process

Method of making NMOS and PMOS devices with reduced masking steps

Transistor with buried insulative layer beneath the channel region

Method of channel doping using diffusion from implanted polysilicon

Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant

Integrated circuit gate conductor which uses layered spacers to produce a graded junction

Multiple split gate semiconductor device and fabrication method

Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion

Trench transistor with insulative spacers

Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions

Method of fabricating a transistor with a dielectric underlayer and device incorporating same

Transistor having a barrier layer below a high permittivity gate dielectric

Method of making an IGFET with a multilevel gate

Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device

Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure

Reticle that compensates for radiation-induced lens error in a photolithographic system

Integrated circuit gate conductor which uses layered spacers to produce a graded junction

Individually controllable radiation sources for providing an image pattern in a photolithographic system

Multiple spacer formation/removal technique for forming a graded junction

Method of forming a shallow junction by diffusion from a silicon-based spacer

Semiconductor wafer with enhanced pre-process denudation and process-induced gettering

Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions

Semiconductor device with vertical halo region and methods of manufacture

Strained-silicon devices with different silicon thicknesses

Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents

Tri-level segmented control transistor and fabrication method

Tilted counter-doped implant to sharpen halo profile

Photolithographic system including light filter that compensates for lens error

Dopant diffusion-retarding barrier region formed within polysilicon gate layer

Angled halo implant tailoring using implant mask

Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls

Method of forming an insulated-gate field-effect transistor with metal spacers

Transistor formation with local interconnect overetch immunity

System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication

Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance

Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant

Transistor with integrated poly/metal gate electrode

CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions

Multiple spacer formation/removal technique for forming a graded junction

Method of forming trench transistor with insulative spacers

Method of making an IGFET and a protected resistor with reduced processing steps

Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls

Ion implantation into a gate electrode layer using an implant profile displacement layer

Method for making asymmetrical N-channel and symmetrical P-channel devices

AMD INC ADVANCED MICRO DEVICES

Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication