Inventor

BAUMGARTNER JASON RAYMOND

US70 patents

⚠️ This page may combine multiple inventors who share the name “BAUMGARTNER JASON RAYMOND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAUMGARTNER JASON RAYMOND

IBM

Method and system for compressing data which allows access to data without full uncompression

Method and system for optimizing systems with enhanced debugging information

Digital circuit verification

High performance voice transformation apparatus and method

Exploiting suspected redundancy for enhanced design verification

Method for automatically generating behavioral environment for model checking

Method and system for parametric reduction of sequential designs

Method for verification using reachability overapproximation

Method for preserving constraints during sequential reparameterization

Method and system of audio file searching

Apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs

Method and system for enhanced design validation through trace tailoring

Method and system for formal characterization of average performance

Method and system for compressing files utilizing a dictionary array

Method and system for error detection in test units utilizing pseudo-random data

Framework for multiple-engine based verification tools for integrated circuits

Method, apparatus, and program for multiple clock domain partitioning through retiming

Reduction of arbitrary L1-L2 circuits for enhanced verification

Reversing the effects of sequential reparameterization on traces

Computer program product for extending incremental verification of circuit design to encompass verification restraints

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Parametric reduction of sequential design

Using constraints in design verification

Generating multimedia information from text information using customized dictionaries

Method for heuristic preservation of critical inputs during sequential reparameterization

Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables

Method and system for reversing the effects of sequential reparameterization on traces

Method and system for reduction of XOR/XNOR subexpressions in structural design representations

Method and system for optimized handling of constraints during symbolic simulation

System and method for engine-controlled case splitting within multiple-engine based verification framework

Method for retiming in the presence of verification constraints

Apparatus and method for representing gated-clock latches for phase abstraction

Use of time step information in a design verification system

Fully exhibiting asynchronous behavior in a logic network simulation

Method and system for reversing the effects of sequential reparameterization on traces

Extending incremental verification of circuit design to encompass verification restraints

System for verification using reachability overapproximation

Method for incremental design reduction via iterative overapproximation and re-encoding strategies

Method and system for enhanced verification through structural target decomposition

Method and system for enhanced verification through binary decision diagram-based target decomposition

Incremental, assertion-based design verification

Apparatus and method for removing effects of phase abstraction from a phase abstracted trace

Dictionary based video compression

Method and system for compressing a state table that allows use of the state table without full uncompression

Method, system and computer program product for verification of digital designs using case-splitting via constrained internal signals

Apparatus and methods for dynamic simulation event triggering

Method for reconfiguration of random biases in a synthesized design without recompilation

Grouping and partitioning of properties for logic verification

(unassigned)

Digital circuit verification with automated specification enumeration