Apparatus and method for removing effects of phase abstraction from a phase abstracted trace

Abstract

An apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs is provided. With the apparatus and method, latches are “colored,” i.e. classified into different types, based on information obtained from a clock tree of the circuit design. Clock tree primitives contain sufficient information to taxonomize the clocks into their respective phases and identify which latches are gated latches. In coloring the latches, gated latches are replaced in the circuit design with a free running clock, a multiplexor, and a sequence of L 1 to Ln latches to provide a feedback path via the data path. This allows the gated latch to be phase abstracted without losing the “gated” functionality of the gated latch in the resulting trace. Once the latches are colored in this way, phase abstraction is performed on the colored circuit design. The phase abstracted netlist is then subjected to verification and a trace is produced. The coloring information of the original circuit, plus information as to the exact nature of the phase abstraction performed, is then used to transform the phase abstracted trace to one which resembles a trace of the circuit without phase abstraction.

What is claimed is:  
     
       1. A method of verifying a circuit design, comprising: 
       performing phase abstraction on the circuit design to generate a phase abstracted circuit design;  
       generating a phase-abstracted trace of the circuit design;  
       automatically removing effects of phase abstraction from the phase-abstracted trace to generate an un-phase-abstracted trace of the circuit design; and  
       verifying the circuit design based on the un-phase-abstracted trace of the circuit design.  
     
     
       2. The method of  claim 1 , wherein automatically removing effects of phase abstraction from the phase-abstracted trace includes replicating signal values in the phase-abstracted trace at determined time periods in the un-phase-abstracted trace. 
     
     
       3. The method of  claim 1 , wherein automatically removing effects of phase abstraction from the phase-abstracted trace includes: 
       receiving coloring information for elements of the circuit design;  
       receiving phase abstraction information identifying which color of elements were preserved during the phase abstraction; and  
       removing effects of phase abstraction from the phase-abstracted trace based on the coloring information and the phase abstraction information.  
     
     
       4. The method of  claim 3 , wherein automatically removing effects of phase abstraction includes: 
       replicating signal values in the phase-abstracted trace at determined timesteps.  
     
     
       5. The method of  claim 4 , wherein the timesteps are determined based on the following relation: 
       
         
             i′=[k *( i− 1)+color( v )+δ( v ), . . . ,  k *( i )+color( v )−1+δ( v )] 
         
       
       where i′ is a set of timesteps, i is a timestep, k is a number of phases in the circuit design, v is a net in a netlist of the circuit design, color(v) is a color of the net v, and δ(v) is a delay value associated with the net.  
     
     
       6. The method of  claim 5 , wherein a value of δ(v) is k only if a color of a circuit element preserved by phase abstraction is greater than color(v), otherwise the value of δ(v) is 0. 
     
     
       7. The method of  claim 5 , wherein if i is less than 0, the signal value is not replicated for that timestep i. 
     
     
       8. The method of  claim 5 , wherein if for a particular timestep i, color(v)=k−1 or i≧color(v), the signal value is not replicated for that timestep i. 
     
     
       9. The method of  claim 1 , wherein automatically removing effects of phase abstraction from the phase-abstracted trace includes: 
       generating a list of signal names of each circuit element color; and  
       selecting signals from the list of signal names to include in the un-phase-abstracted trace.  
     
     
       10. The method of  claim 9 , wherein the signals are selected such that values of functional logic in the circuit design are preserved in the un-phase-abstracted trace while clock tree logic is not included in the un-phase-abstracted trace. 
     
     
       11. A computer program product in a computer readable medium for verifying a circuit design, comprising: 
       first instructions for performing phase abstraction on the circuit design to generate a phase abstracted circuit design;  
       second instructions for generating a phase-abstracted trace of the circuit design;  
       third instructions for automatically removing effects of phase abstraction from the phase-abstracted trace to generate an un-phase-abstracted trace of the circuit design; and  
       fourth instructions for verifying the circuit design based on the un-phase-abstracted trace of the circuit design.  
     
     
       12. The computer program product of  claim 11 , wherein the third instructions for automatically removing effects of phase abstraction from the phase-abstracted trace include instructions for replicating signal values in the phase-abstracted trace at determined time periods in the un-phase-abstracted trace. 
     
     
       13. The computer program product of  claim 11 , wherein the third instructions for automatically removing effects of phase abstraction from the phase-abstracted trace include: 
       instructions for receiving coloring information for elements of the circuit design;  
       instructions for receiving phase abstraction information identifying which color of elements were preserved during the phase abstraction; and  
       instructions for removing effects of phase abstraction from the phase-abstracted trace based on the coloring information and the phase abstraction information.  
     
     
       14. The computer program product of  claim 13 , wherein the third instructions for automatically removing effects of phase abstraction include: 
       instructions for replicating signal values in the phase-abstracted trace at determined timesteps.  
     
     
       15. The computer program product of  claim 14 , wherein the timesteps are determined based on the following relation: 
       
         
             i′=[k *( i− 1)+color( v )+δ( v ), . . . ,  k *( i )+color( v )−1+δ( v )] 
         
       
       where i′ is a set of timesteps, i is a timestep, k is a number of phases in the circuit design, v is a net in a netlist of the circuit design, color(v) is a color of the net v, and δ(v) is a delay value associated with the net.  
     
     
       16. The computer program product of  claim 15 , wherein a value of δ(v) is k only if a color of a circuit element preserved by phase abstraction is greater than color(v), otherwise the value of δ(v) is 0. 
     
     
       17. The computer program product of  claim 15 , wherein if i is less than 0, the signal value is not replicated for that timestep i. 
     
     
       18. The computer program product of  claim 15 , wherein if for a particular timestep i, color(v)=k−1 or i≧color(v), the signal value is not replicated for that timestep i. 
     
     
       19. The computer program product of  claim 11 , wherein the third instructions for automatically removing effects of phase abstraction from the phase-abstracted trace include: 
       instructions for generating a list of signal names of each circuit element color; and  
       instructions for selecting signals from the list of signal names to include in the un-phase-abstracted trace.  
     
     
       20. The computer program product of  claim 19 , wherein the signals are selected such that values of functional logic in the circuit design are preserved in the un-phase-abstracted trace while clock tree logic is not included in the un-phase-abstracted trace. 
     
     
       21. An apparatus for verifying a circuit design, comprising: 
       means for performing phase abstraction on the circuit design to generate a phase abstracted circuit design;  
       means for generating a phase-abstracted trace of the circuit design;  
       means for automatically removing effects of phase abstraction from the phase-abstracted trace to generate an un-phase-abstracted trace of the circuit design; and  
       means for verifying the circuit design based on the un-phase-abstracted trace of the circuit design.  
     
     
       22. The apparatus of  claim 21 , wherein the means for automatically removing effects of phase abstraction from the phase-abstracted trace includes means for replicating signal values in the phase-abstracted trace at determined time periods in the un-phase-abstracted trace. 
     
     
       23. The apparatus of  claim 21 , wherein the means for automatically removing effects of phase abstraction from the phase-abstracted trace includes: 
       means for receiving coloring information for elements of the circuit design;  
       means for receiving phase abstraction information identifying which color of elements were preserved during the phase abstraction; and  
       means for removing effects of phase abstraction from the phase-abstracted trace based on the coloring information and the phase abstraction information.  
     
     
       24. The apparatus of  claim 23 , wherein the means for automatically removing effects of phase abstraction includes: 
       means for replicating signal values in the phase-abstracted trace at determined timesteps.  
     
     
       25. The apparatus of  claim 24 , wherein the timesteps are determined based on the following relation: 
       
         
             i′=[k *( i− 1)+color( v )+δ( v ), . . . ,  k *( i )+color( v )−1+δ( v )] 
         
       
       where i′ is a set of timesteps, i is a timestep, k is number of phases in the circuit design, v is a net in a netlist of the circuit design, color(v) is a color of the net v, and δ(v) is a delay value associated with the net.  
     
     
       26. The apparatus of  claim 25 , wherein a value of δ(v) is k only if a color of a circuit element preserved by phase abstraction is greater than color(v), otherwise the value of δ(v) is 0. 
     
     
       27. The apparatus of  claim 25 , wherein if i is less than 0, the signal value is not replicated for that timestep i. 
     
     
       28. The apparatus of  claim 25 , wherein if for a particular timestep i, color(v)=k−1 or i≧color(v), the signal value is not replicated for that timestep i. 
     
     
       29. The apparatus of  claim 21 , wherein the means for automatically removing effects of phase abstraction from the phase-abstracted trace includes: 
       means for generating a list of signal names of each circuit element color; and  
       means for selecting signals from the list of signal names to include in the un-phase-abstracted trace.  
     
     
       30. The apparatus of  claim 29 , wherein the signals are selected such that values of functional logic in the circuit design are preserved in the un-phase-abstracted trace while clock tree logic is not included in the un-phase-abstracted trace.