Inventor
KANZELMAN ROBERT LOWELL
US26 patents
Patents
26 patentsUS7260799B2Aug 21, 2007
Exploiting suspected redundancy for enhanced design verification
IBM21 citations93
US6763505B2Jul 13, 2004
Apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs
IBM26 citations92
US5799170AAug 25, 1998
Simplified buffer manipulation using standard repowering function
IBM21 citations91
US7779378B2Aug 17, 2010
Computer program product for extending incremental verification of circuit design to encompass verification restraints
IBM8 citations84
US7340694B2Mar 4, 2008
Method and system for reduction of XOR/XNOR subexpressions in structural design representations
IBM9 citations84
US7266795B2Sep 4, 2007
System and method for engine-controlled case splitting within multiple-engine based verification framework
IBM10 citations84
US6745377B2Jun 1, 2004
Apparatus and method for representing gated-clock latches for phase abstraction
IBM15 citations84
US7360185B2Apr 15, 2008
Design verification using sequential and combinational transformations
IBM11 citations82
US7210109B2Apr 24, 2007
Equivalence checking of scan path flush operations
IBM15 citations76
US7509605B2Mar 24, 2009
Extending incremental verification of circuit design to encompass verification restraints
IBM7 citations74
US7370292B2May 6, 2008
Method for incremental design reduction via iterative overapproximation and re-encoding strategies
IBM8 citations74
US7350169B2Mar 25, 2008
Method and system for enhanced verification through structural target decomposition
IBM8 citations74
US7343573B2Mar 11, 2008
Method and system for enhanced verification through binary decision diagram-based target decomposition
IBM5 citations74
US7093218B2Aug 15, 2006
Incremental, assertion-based design verification
IBM8 citations74
US6748573B2Jun 8, 2004
Apparatus and method for removing effects of phase abstraction from a phase abstracted trace
IBM12 citations74
US7921394B2Apr 5, 2011
Enhanced verification through binary decision diagram-based target decomposition
IBM3 citations63
US7913218B2Mar 22, 2011
Reduction of XOR/XNOR subexpressions in structural design representations
IBM1 citations63
US7908575B2Mar 15, 2011
Enhanced verification through binary decision diagram-based target decomposition using state analysis extraction
IBM2 citations63
US7831937B2Nov 9, 2010
Method and system for reduction of XOR/XNOR subexpressions in structural design representations
IBM2 citations63
US7823093B2Oct 26, 2010
Method and system for reduction of and/or subexpressions in structural design representations
IBM2 citations63
US7380221B2May 27, 2008
Method and system for reduction of and/or subexpressions in structural design representations
IBM3 citations63
US7996800B2Aug 9, 2011
Computer program product for design verification using sequential and combinational transformations
IBM5 citations60
US11922130B2Mar 5, 2024
Optimization of arithmetic expressions
IBM1 citations59
US7930672B2Apr 19, 2011
Incremental design reduction via iterative overapproximation and re-encoding strategies
IBM1 citations52
US7882459B2Feb 1, 2011
Method and system for reduction of AND/OR subexpressions in structural design representations
IBM0 citations52
US12475287B2Nov 18, 2025
Equivalence checking of synthesized logic designs using generated synthesis history
IBM0 citations49