Inventor

WU ALBERT

US105 patents

⚠️ This page may combine multiple inventors who share the name “WU ALBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU ALBERT

MARVELL INT LTD

Memory repair system and method

Method and system for memory testing and test data reporting during memory testing

Memory repair system and method

Method to form high density phase change memory (PCM) top contact every two bits

Fuse structures, methods of making and using the same, and integrated circuits including the same

Heat dissipating interposers

System and method for creating a bipolar resistive RAM (RRAM)

Integrated circuit packaging configurations

Apparatus and method for remapping addresses of defective memory locations to redundant memory locations

Pre-formed conductive bumps on bonding pads

High density via and metal interconnect structures, and methods of forming the same

Self aligned integration of high density phase change memory with thin film access device

Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips

High-density contact holes

Method and system for memory testing and test data reporting during memory testing

Methods of making and using fuse structures, and integrated circuits including the same

Memory repair system and method

Fuse structures, methods of making and using the same, and integrated circuits including the same

MARVELL WORLD TRADE LTD

Stack die packages

Structures embedded within core material and methods of manufacturing thereof

Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell

Phase change material (PCM) memory devices with bipolar junction transistors and methods for making thereof

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

Method for fabricating 1T-DRAM on bulk silicon

Alpha shielding techniques and configurations

Semiconductor packaging with internal wiring bus

Method and apparatus for improving the reliability of a connection to a via in a substrate

Method and apparatus for incorporating passive devices in an integrated passive device separate from a die

Package assembly having a semiconductor substrate

Apparatus and method for reforming resistive memory cells

WU ALBERT

Insole cushioning device with repelling magnetic field

Reducing source contact to gate spacing to decrease transistor pitch

Memory repair system and method

Test engine for integrated circuit chip testing

Memory repair system and method

High resistivity substrate for integrated passive device (IPD) applications

INTEGRATED SILICON SOLUTION

Method of making an EEPROM

Non-volatile semiconductor memory cell

Non-volatile semiconductor memory cell

LIOU SHIANN-MING

Integrated circuit packaging configurations

Pre-formed conductive bumps on bonding pads

SUTARDJA SEHAT

Structures embedded within core material and methods of manufacturing thereof

Semiconductor package including a power plane and a ground plane

CLARITI TELECOMMUNICATIONS INT

Multiple subcarrier communication system

Digital compressed voice paging system which uses R.D.S. format for the ID signals and S.C.A. format for the voice signals both formats being FM subcarriers

NIO USA INC

Systems and methods of autonomously controlling vehicle lane change maneuver

Vehicle control system using nonlinear dynamic model states and steering offset estimation

WINBOND ELECTRONICS CORP I

Semiconductor memory array with buried drain lines and methods therefor

MEGIC CORP

Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits

LEE WINSTON

Method and systems for memory testing and test data reporting during memory testing