Inventor

CHANG RUNZI

US67 patents

⚠️ This page may combine multiple inventors who share the name “CHANG RUNZI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG RUNZI

MARVELL WORLD TRADE LTD

Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

Apparatus and methods for temperature-based memory management

Isolation components for transistors formed on fin features of semiconductor substrates

Methods and systems to improve yield in multiple chips integration processes

Apparatus and method for reforming resistive memory cells

Fabricating memory devices with optimized gate oxide thickness

Resistive random access memory cell structure

Resistive random access memory cell structure with reduced programming voltage

Systems and methods for reading resistive random access memory (RRAM) cells

Method to form high efficiency GST cell using a double heater cut

Method to form high efficiency GST cell using a double heater cut

Creating an aligned via and metal line in an integrated circuit including forming an oversized via mask

Sub-device field-effect transistor architecture for integrated circuits

Isolation components for transistors formed on fin features of semiconductor substrates

Fabricating memory devices with optimized gate oxide thickness

Methods and systems for packaging semiconductor devices to improve yield

MARVELL INT LTD

Method to form high density phase change memory (PCM) top contact every two bits

Photolithography mask design-rule check assistance

System and method for creating a bipolar resistive RAM (RRAM)

High density via and metal interconnect structures, and methods of forming the same

Self aligned integration of high density phase change memory with thin film access device

Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips

Mobile storage system for storing and transferring data generated by Internet of Things (IoT) devices

Modular memory-like layout for finFET analog designs

Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM)

Resistive memory cell and method for forming a resistive memory cell

High-density patterning

Methods to form wide heater trenches and to form memory cells to engage heaters

Low base resistance bipolar junction transistor array

Ion implantation and process sequence to form smaller base pick-up

MRAM structure for efficient manufacturability

MARVELL ASIA PTE LTD

Real-time, in-situ reliability monitoring in an integrated circuit

Electrical performance and reliability of a semiconductor device comprising continuous diffusion structures

Systems and methods for configuring a central processing unit having multiple cores

Systems and methods for forming finFET analog designs having a modular memory-like layout

Methods and systems for packaging an integrated circuit

Gate stack for metal gate transistor

Gate stack for metal gate transistor

Through-silicon via for high-speed interconnects

Electronic fuse (eFuse) designs for enhanced chip security

Three-dimensional integration of processing chiplet and static random-access memory (SRAM) chiplets

Double seal ring and electrical connection of multiple chiplets

Performance of magnetic channel junctions

Device having bipolar junction transistors and finFET transistors on the same substrate

Decoupling capacitor integrated in system on chip (SOC) device

WU ALBERT

Reducing source contact to gate spacing to decrease transistor pitch

Method for shallow trench isolation

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

SUTARDJA PANTAS

Method for creating ultra-high-density holes and metallization