Inventor

LEE WINSTON

US88 patents

⚠️ This page may combine multiple inventors who share the name “LEE WINSTON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE WINSTON

MARVELL INT LTD

Method and system for memory testing and test data reporting during memory testing

Logic process DRAM

Logic process DRAM

Logic process DRAM

Banked physical register data flow architecture in out-of-order processors

Method to form high density phase change memory (PCM) top contact every two bits

System and method for creating a bipolar resistive RAM (RRAM)

High density via and metal interconnect structures, and methods of forming the same

Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips

Banked physical register data flow architecture in out-of-order processors

Method and system for memory testing and test data reporting during memory testing

Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes

Test data reporting during memory testing

Phase change memory array circuits and methods of manufacture

Logic process DRAM

Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes

Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM)

Resistive memory cell and method for forming a resistive memory cell

High-density patterning

Methods to form wide heater trenches and to form memory cells to engage heaters

MARVELL WORLD TRADE LTD

System and method for memory array decoding

Multiport memory architecture, devices and systems including the same, and methods of using the same

Concurrent use of SRAM cells with both NMOS and PMOS pass gates in a memory system

Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell

Multiport memory architecture

Methods and systems to improve yield in multiple chips integration processes

Apparatus and method for reforming resistive memory cells

Fabricating memory devices with optimized gate oxide thickness

Resistive random access memory cell structure

Resistive random access memory cell structure with reduced programming voltage

Systems and methods for reading resistive random access memory (RRAM) cells

SRAM cells suitable for Fin field-effect transistor (FinFET) process

MONOLITHIC SYSTEM TECH INC

Memory array with read/write methods

Dynamic address mapping and redundancy in a modular memory device

Resynchronization circuit for a memory system and method of operating same

Reduced CMOS-swing clamping circuit for bus lines

Data processing system with master and slave devices and asymmetric signal swing bus

Termination circuits for reduced swing signal lines and methods for operating same

Resynchronization circuit for circuit module architecture

LEE WINSTON

Multiport memory architecture, devices and systems including the same, and methods of using the same

Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes

Circuits and methods for calibrating offset in an amplifier

Method and systems for memory testing and test data reporting during memory testing

SUNDISK CORP

Latent defect handling in EEPROM devices

Multi-state EEprom read and write circuits and techniques

Multi-state EEprom read and write circuits and techniques

SANDISK CORP

Latent defect handling in EEPROM devices

WU ALBERT

Reducing source contact to gate spacing to decrease transistor pitch

DEGIRUM CORP

Permutated ring network

MARVELL ASIA PTE LTD

Methods and systems for packaging an integrated circuit