Inventor

ZORIAN YERVANT

US48 patents

⚠️ This page may combine multiple inventors who share the name “ZORIAN YERVANT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZORIAN YERVANT

SYNOPSYS INC

Architecture, system and method for compressing repair data in an integrated circuit (IC) design

Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer

Methods and apparatuses for external test methodology and initialization of input-output circuits

FinFET-based memory testing using multiple read operations

Periodic signal measurement using statistical sampling

Detection of address errors in memory devices using multi-segment error detection codes

Methods and apparatuses for external voltage test of input-output circuits

Diagnosing faults in memory periphery circuitry

Embedded memory transparent in-system built-in self-test

Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer

On-chip memory diagnostics

In situ delay measurements on integrated circuits using live data and pulse width modulation

Built-in self-test circuit for row hammering in memory

FinFET-based memory testing using multiple read operations

Testing electronic memories based on fault and test algorithm periodicity

Method and apparatus for SOC with optimal RSMA

VIRAGE LOGIC CORP

Methods and apparatuses that reduce the size of a repair data container for repairable memories

Methods and apparatuses for external delay test of input-output circuits

Apparatus, method, and system to allocate redundant components

Apparatus and method to generate a repair signature

Apparatus, method, and system having a pin to activate the self-test and repair instructions

System and method for repairing a memory

Method and apparatus for a command based bist for testing memories

Apparatus, method, and system to allocate redundant components with subsets of the redundant components

System and method for verifying IP integrity in system-on-chip (SOC) design

Input-output device testing

Memory modeling using an intermediate level structural description

System and method for repairing a memory

LUCENT TECHNOLOGIES INC

Optimized built-in self-test method and apparatus for random access memories

Built-in self-test control network

Method for built-in self-testing of ring-address FIFOs having a data input register with transparent latches

Built-in self-test in a plurality of stages controlled by a token passing network and method

Built-in self-test controlled by a token network and method

Built in shelf test method and apparatus for booth multipliers

AGERE SYST GUARDIAN CORP

System and method for detecting faults in computer memories using a look up table

Built-in self-test and self-repair methods and devices for computer memories comprising a reconfiguration memory device

Self-testing of DRAMs for multiple faults

AT & T BELL LAB

Built-in self-test technique for content-addressable memories

Built-in self-test technique for read-only memories

AT & T CORP

Method and apparatus for detecting retention faults in memories

Method for built-in self-testing of ring-address FIFOs

AMIRKHANYAN KAREN

Detecting random telegraph noise induced failures in an electronic memory

Generation of memory structural model based on memory layout

ZORIAN YERVANT

Memory hard macro partition optimization for testing embedded memories

ALEKSANYAN KAREN

Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers

TABATABAEI SASSAN

Methods and apparatuses for external voltage test methodology of input-output circuits

DARBINYAN KAREN

Architecture, system and method for compressing repair data in an integrated circuit (IC) design

GRIGORYAN HAYK

Determining a desirable number of segments for a multi-segment single error correcting coding scheme