Inventor

BATTLE STEVEN J

US39 patents

Patents

39 patents

US11144319B1Oct 12, 2021

Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry

IBM0 citations62

US11093282B2Aug 17, 2021

Register file write using pointers

IBM0 citations62

US11061681B2Jul 13, 2021

Instruction streaming using copy select vector

IBM0 citations62

US10996995B2May 4, 2021

Saving and restoring a transaction memory state

IBM0 citations62

US10545765B2Jan 28, 2020

Multi-level history buffer for transaction memory in a microprocessor

IBM1 citations62

US10379867B2Aug 13, 2019

Asynchronous flush and restore of distributed history buffer

IBM1 citations62

US11360779B2Jun 14, 2022

Logical register recovery within a processor

IBM0 citations61

US11327757B2May 10, 2022

Processor providing intelligent management of values buffered in overlaid architected and non-architected register files

IBM0 citations61

US11194578B2Dec 7, 2021

Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor

IBM0 citations61

US11163568B2Nov 2, 2021

Implementing write ports in register-file array cell

IBM1 citations61

US11144364B2Oct 12, 2021

Supporting speculative microprocessor instruction execution

IBM1 citations60

US10956158B2Mar 23, 2021

System and handling of register data in processors

IBM0 citations60

US10949205B2Mar 16, 2021

Implementation of execution compression of instructions in slice target register file mapper

IBM1 citations58

US11561794B2Jan 24, 2023

Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry

IBM0 citations52

US10909034B2Feb 2, 2021

Issue queue snooping for asynchronous flush and restore of distributed history buffer

IBM0 citations52

US11709676B2Jul 25, 2023

Inferring future value for speculative branch resolution

IBM0 citations51

US11188332B2Nov 30, 2021

System and handling of register data in processors

IBM0 citations51

US10564691B2Feb 18, 2020

Reducing power consumption in a multi-slice computer processor

IBM0 citations51

US10489253B2Nov 26, 2019

On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor

IBM0 citations51

US10209757B2Feb 19, 2019

Reducing power consumption in a multi-slice computer processor

IBM0 citations51

US9870039B2Jan 16, 2018

Reducing power consumption in a multi-slice computer processor

IBM0 citations51

US11068267B2Jul 20, 2021

High bandwidth logical register flush recovery

IBM0 citations49

US11030018B2Jun 8, 2021

On-demand multi-tiered hang buster for SMT microprocessor

IBM0 citations49

US11403109B2Aug 2, 2022

Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor

IBM0 citations48

US10740140B2Aug 11, 2020

Flush-recovery bandwidth in a processor

IBM0 citations48

US10296337B2May 21, 2019

Preventing premature reads from a general purpose register

IBM0 citations40

US10127121B2Nov 13, 2018

Operation of a multi-slice processor implementing adaptive failure state capture

IBM0 citations37

BATTLE STEVEN J

Patents

Redistribution of architected states for a processor register file

Check pointing of accumulator register results in a microprocessor

Logical register recovery within a processor

Reducing power consumption in a multi-slice computer processor

Direct register restore mechanism for distributed history buffers

Adaptive debug tracing for microprocessors

Assignment of microprocessor register tags at issue time

Fast mapper restore for flush in processor

Inferring future value for speculative branch resolution in a microprocessor

Compaction of architected registers in a simultaneous multithreading processor

Assignment of microprocessor register tags at issue time

Instruction streaming using state migration

Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry

Register file write using pointers

Instruction streaming using copy select vector

Saving and restoring a transaction memory state

Multi-level history buffer for transaction memory in a microprocessor

Asynchronous flush and restore of distributed history buffer

Logical register recovery within a processor

Processor providing intelligent management of values buffered in overlaid architected and non-architected register files

Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor

Implementing write ports in register-file array cell

Supporting speculative microprocessor instruction execution

System and handling of register data in processors

Implementation of execution compression of instructions in slice target register file mapper

Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entry

Issue queue snooping for asynchronous flush and restore of distributed history buffer

Inferring future value for speculative branch resolution

System and handling of register data in processors

Reducing power consumption in a multi-slice computer processor

On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessor

Reducing power consumption in a multi-slice computer processor

Reducing power consumption in a multi-slice computer processor

High bandwidth logical register flush recovery

On-demand multi-tiered hang buster for SMT microprocessor

Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processor

Flush-recovery bandwidth in a processor

Preventing premature reads from a general purpose register

Operation of a multi-slice processor implementing adaptive failure state capture