Inferring future value for speculative branch resolution

Abstract

Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.

What is claimed is: 
     
       1. A computer-implemented method comprising:
 determining a first instruction in a processing pipeline, wherein the first instruction comprises a compare instruction; 
 determining a second instruction in the processing pipeline, wherein the second instruction comprises a conditional branch instruction relying on the compare instruction; 
 determining a predicted result of the compare instruction; 
 completing the conditional branch instruction using the predicted result prior to executing the compare instruction; 
 writing a first instruction tag into a conditional register mapper comprising one or more individually addressable N-bit fields; 
 setting a first bit to one in a first N-bit field of the conditional register mapper based on the first instruction comprising a compare instruction; 
 setting a second bit to zero in the first N-bit field of the conditional register mapper based on the first instruction not being executed and written back; and 
 responsive to the first bit having a value of one and the second bit having a value of zero in the first N-bit field of the conditional register mapper, writing the first instruction tag read out from the conditional register mapper into a first field of a compare info queue. 
 
     
     
       2. The computer-implement method of  claim 1 , further comprising executing the compare instruction to determine a calculated result. 
     
     
       3. The computer-implemented method of  claim 2 , further comprising:
 determining a branch miss based on the calculated result not matching the predicted result; and 
 performing a pipeline flush responsive to the branch miss. 
 
     
     
       4. The computer-implemented method of  claim 1 , wherein the predicted result of the compare instruction is determined based on a branch prediction algorithm. 
     
     
       5. The computer-implemented method of  claim 1 , further comprising:
 writing the predicted result of the compare instruction to a second field of the compare info queue, wherein the compare info queue comprises a register. 
 
     
     
       6. The computer-implemented method of  claim 1 , wherein the first instruction is written into an issue queue. 
     
     
       7. A system comprising:
 a memory having computer readable instructions; and 
 one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
 determining a first instruction in a processing pipeline, wherein the first instruction comprises a compare instruction; 
 determining a second instruction in the processing pipeline, wherein the second instruction comprises a conditional branch instruction relying on the compare instruction; 
 determining a predicted result of the compare instruction; 
 completing the conditional branch instruction using the predicted result prior to executing the compare instruction; 
 writing a first instruction tag into a conditional register mapper comprising one or more individually addressable N-bit fields; 
 setting a first bit to one in a first N-bit field of the conditional register mapper based on the first instruction comprising a compare instruction; 
 setting a second bit to zero in the first N-bit field of the conditional register matter based on the first instruction not being executed and written back; and 
 responsive to the first bit having a value of one and the second bit having a value of zero in the first N-bit field of the conditional register mapper, writing the first instruction tag read out from the conditional register mapper into a first field of a compare info queue. 
 
 
     
     
       8. The system of  claim 7 , wherein the operations further comprise: executing the compare instruction to determine a calculated result. 
     
     
       9. The system of  claim 8 , wherein the operations further comprise:
 determining a branch miss based on the calculated result not matching the predicted result; and 
 performing a pipeline flush responsive to the branch miss. 
 
     
     
       10. The system of  claim 7 , wherein the predicted result of the compare instruction is determined based on a branch prediction algorithm. 
     
     
       11. The system of  claim 7 , wherein the operations further comprise:
 writing the predicted result of the compare instruction to a second field of the compare info queue, wherein the compare info queue comprises a register. 
 
     
     
       12. The system of  claim 7 , wherein the first instruction is written into an issue queue. 
     
     
       13. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:
 determining a first instruction in a processing pipeline, wherein the first instruction comprises a compare instruction; 
 determining a second instruction in the processing pipeline, wherein the second instruction comprises a conditional branch instruction relying on the compare instruction; 
 determining a predicted result of the compare instruction; 
 completing the conditional branch instruction using the predicted result; 
 writing a first instruction tag into a conditional register mapper comprising one or more individually addressable N-bit fields; 
 setting a first bit to one in a first N-bit field of the conditional register mapper based on the first instruction comprising a compare instruction; 
 setting a second bit to zero in the first N-bit field of the conditional register matter based on the first instruction not being executed and written back; and 
 responsive to the first bit having a value of one and the second bit having a value of zero in the first N-bit field of the conditional register mapper, writing the first instruction tag read out from the conditional register mapper into a first field of a compare info queue. 
 
     
     
       14. The computer program product of  claim 13 , wherein the operations further comprise: executing the compare instruction to determine a calculated result. 
     
     
       15. The computer program product of  claim 14 , wherein the operations further comprise:
 determining a branch miss based on the calculated result not matching the predicted result; and 
 performing a pipeline flush responsive to the branch miss. 
 
     
     
       16. The computer program product of  claim 13 , wherein the predicted result of the compare instruction is determined based on a branch prediction algorithm. 
     
     
       17. The computer program product of  claim 13 , wherein the operations further comprise:
 writing the predicted result of the compare instruction to a second field of the compare info queue, wherein the compare info queue comprises a register. 
 
     
     
       18. The computer program product of  claim 13 , wherein the first instruction is written into an issue queue.